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d4c615be8c
Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
134 lines
3.5 KiB
LLVM
134 lines
3.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
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; InstCombine and DAGCombiner transform an 'add' into an 'or'
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; if there are no common bits from the incoming operands.
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; LEA instruction selection should be able to see through that
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; transform and reduce add/shift/or instruction counts.
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define i32 @or_shift1_and1(i32 %x, i32 %y) {
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; CHECK-LABEL: or_shift1_and1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
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; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
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; CHECK-NEXT: andl $1, %esi
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; CHECK-NEXT: leal (%rsi,%rdi,2), %eax
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; CHECK-NEXT: retq
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%shl = shl i32 %x, 1
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%and = and i32 %y, 1
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%or = or i32 %and, %shl
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ret i32 %or
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}
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define i32 @or_shift1_and1_swapped(i32 %x, i32 %y) {
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; CHECK-LABEL: or_shift1_and1_swapped:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
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; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
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; CHECK-NEXT: andl $1, %esi
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; CHECK-NEXT: leal (%rsi,%rdi,2), %eax
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; CHECK-NEXT: retq
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%shl = shl i32 %x, 1
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%and = and i32 %y, 1
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%or = or i32 %shl, %and
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ret i32 %or
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}
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define i32 @or_shift2_and1(i32 %x, i32 %y) {
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; CHECK-LABEL: or_shift2_and1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
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; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
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; CHECK-NEXT: andl $1, %esi
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; CHECK-NEXT: leal (%rsi,%rdi,4), %eax
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; CHECK-NEXT: retq
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%shl = shl i32 %x, 2
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%and = and i32 %y, 1
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%or = or i32 %shl, %and
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ret i32 %or
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}
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define i32 @or_shift3_and1(i32 %x, i32 %y) {
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; CHECK-LABEL: or_shift3_and1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
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; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
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; CHECK-NEXT: andl $1, %esi
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; CHECK-NEXT: leal (%rsi,%rdi,8), %eax
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; CHECK-NEXT: retq
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%shl = shl i32 %x, 3
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%and = and i32 %y, 1
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%or = or i32 %shl, %and
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ret i32 %or
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}
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define i32 @or_shift3_and7(i32 %x, i32 %y) {
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; CHECK-LABEL: or_shift3_and7:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
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; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
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; CHECK-NEXT: andl $7, %esi
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; CHECK-NEXT: leal (%rsi,%rdi,8), %eax
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; CHECK-NEXT: retq
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%shl = shl i32 %x, 3
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%and = and i32 %y, 7
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%or = or i32 %shl, %and
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ret i32 %or
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}
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; The shift is too big for an LEA.
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define i32 @or_shift4_and1(i32 %x, i32 %y) {
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; CHECK-LABEL: or_shift4_and1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
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; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
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; CHECK-NEXT: shll $4, %edi
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; CHECK-NEXT: andl $1, %esi
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; CHECK-NEXT: leal (%rsi,%rdi), %eax
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; CHECK-NEXT: retq
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%shl = shl i32 %x, 4
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%and = and i32 %y, 1
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%or = or i32 %shl, %and
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ret i32 %or
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}
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; The mask is too big for the shift, so the 'or' isn't equivalent to an 'add'.
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define i32 @or_shift3_and8(i32 %x, i32 %y) {
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; CHECK-LABEL: or_shift3_and8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
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; CHECK-NEXT: leal (,%rdi,8), %eax
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; CHECK-NEXT: andl $8, %esi
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; CHECK-NEXT: orl %esi, %eax
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; CHECK-NEXT: retq
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%shl = shl i32 %x, 3
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%and = and i32 %y, 8
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%or = or i32 %shl, %and
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ret i32 %or
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}
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; 64-bit operands should work too.
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define i64 @or_shift1_and1_64(i64 %x, i64 %y) {
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; CHECK-LABEL: or_shift1_and1_64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: andl $1, %esi
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; CHECK-NEXT: leaq (%rsi,%rdi,2), %rax
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; CHECK-NEXT: retq
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%shl = shl i64 %x, 1
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%and = and i64 %y, 1
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%or = or i64 %and, %shl
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ret i64 %or
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}
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