1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-25 12:12:47 +01:00
llvm-mirror/test/MachineVerifier
Jonas Paulsson 2a69f5997d [MachineVerifier] Improve checks of target instructions operands.
While working with a patch for instruction selection, the splitting of a
large immediate ended up begin treated incorrectly by the backend. Where a
register operand should have been created, it instead became an immediate. To
my surprise the machine verifier failed to report this, which at the time
would have been helpful.

This patch improves the verifier so that it will report this type of error.

This patch XFAILs CodeGen/SPARC/fp128.ll, which has been reported at
https://bugs.llvm.org/show_bug.cgi?id=44091

Review: thegameg, arsenm, fhahn
https://reviews.llvm.org/D63973
2019-12-03 10:20:52 +01:00
..
test_copy_mismatch_types.mir
test_copy.mir
test_g_add.mir
test_g_addrspacecast.mir
test_g_bitcast.mir
test_g_brjt.mir
test_g_build_vector_trunc.mir
test_g_build_vector.mir
test_g_concat_vectors.mir
test_g_constant.mir
test_g_dyn_stackalloc.mir
test_g_extract.mir
test_g_fcmp.mir
test_g_fconstant.mir
test_g_icmp.mir
test_g_insert.mir
test_g_intrinsic_w_side_effects.mir
test_g_intrinsic.mir
test_g_inttoptr.mir
test_g_jump_table.mir
test_g_load.mir
test_g_merge_values.mir
test_g_phi.mir
test_g_ptr_add.mir [globalisel] Rename G_GEP to G_PTR_ADD 2019-11-05 10:31:17 -08:00
test_g_ptrtoint.mir
test_g_select.mir
test_g_sext_inreg.mir
test_g_sextload.mir
test_g_shuffle_vector.mir
test_g_store.mir
test_g_trunc.mir
test_g_zextload.mir
test_memccpy_intrinsics.mir
test_phis_precede_nonphis.mir
verifier-generic-extend-truncate.mir
verifier-generic-types-1.mir
verifier-generic-types-2.mir
verifier-implicit-virtreg-invalid-physreg-liveness.mir
verifier-phi-fail0.mir
verifier-phi.mir
verifier-pseudo-terminators.mir
verify-regbankselected.mir
verify-regops.mir [MachineVerifier] Improve checks of target instructions operands. 2019-12-03 10:20:52 +01:00
verify-selected.mir