mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-25 12:12:47 +01:00
3880641c3c
The Verifier is separate from the MachineVerifier, so move it to a different directory. Some other verifier tests were scattered in target codegen tests as well (although I'm sure I missed some). Work towards using a more consistent naming scheme to make it clearer where the gaps still are for generic instructions. llvm-svn: 354138
38 lines
1.0 KiB
YAML
38 lines
1.0 KiB
YAML
#RUN: not llc -march=aarch64 -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
|
|
# REQUIRES: global-isel, aarch64-registered-target
|
|
|
|
---
|
|
name: test_add
|
|
legalized: true
|
|
regBankSelected: false
|
|
selected: false
|
|
tracksRegLiveness: true
|
|
liveins:
|
|
body: |
|
|
bb.0:
|
|
|
|
%0:_(s32) = G_CONSTANT i32 0
|
|
%1:_(s32) = G_CONSTANT i32 1
|
|
|
|
; CHECK: Bad machine code: Too few operands
|
|
%2:_(s32) = G_ADD
|
|
|
|
; CHECK: Bad machine code: Too few operands
|
|
%3:_(s32) = G_ADD %0
|
|
%4:_(s32) = G_ADD %0, %1
|
|
|
|
; CHECK: Bad machine code: Too few operands
|
|
; CHECK: Bad machine code: Explicit definition marked as use
|
|
G_ADD %0, %1
|
|
|
|
; CHECK: Bad machine code: generic instruction must use register operands
|
|
%5:_(s32) = G_ADD %0, 1
|
|
|
|
%6:_(s64) = G_CONSTANT i64 0
|
|
|
|
; CHECK: Bad machine code: Type mismatch in generic instruction
|
|
; CHECK: Bad machine code: Generic virtual register does not allow subregister index
|
|
%8:_(s32) = G_ADD %6.sub_32:_(s64), %0
|
|
|
|
...
|