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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-20 11:33:24 +02:00
llvm-mirror/test/CodeGen
2016-05-10 16:55:20 +00:00
..
AArch64 [AArch64] Implement lowering of the X constraint on AArch64 2016-05-09 11:10:44 +00:00
AMDGPU liveness.mir requires asserts to use -debug-only 2016-05-10 05:38:47 +00:00
ARM [ARM] Fix Scavenger assert due to underestimated stack size 2016-05-08 05:11:54 +00:00
BPF BPF: emit an error message for unsupported signed division operation 2016-03-18 22:02:47 +00:00
Generic llc: Rework -run-pass option 2016-05-10 01:32:44 +00:00
Hexagon [ScheduleDAG] Make sure to process all def operands before any use operands 2016-05-10 16:50:30 +00:00
Inputs [PR27284] Reverse the ownership between DICompileUnit and DISubprogram. 2016-04-15 15:57:41 +00:00
Lanai [lanai] Add subword scheduling itineraries. 2016-04-20 18:28:55 +00:00
Mips [mips][micromips] Make getPointerRegClass() result depend on the instruction. 2016-05-09 13:38:25 +00:00
MIR ARM: fix handling of SUB immediates in peephole opt. 2016-05-02 18:30:08 +00:00
MSP430
NVPTX [NVPTX] Fix sign/zero-extending ldg/ldu instruction selection 2016-05-02 18:12:02 +00:00
PowerPC [Power9] Add support for -mcpu=pwr9 in the back end 2016-05-09 18:54:58 +00:00
SPARC [Sparc][LEON] Itineraries unit test. 2016-05-10 09:09:20 +00:00
SystemZ [PR27599] [SystemZ] [SelectionDAG] Fix extension of atomic cmpxchg result. 2016-05-10 16:49:04 +00:00
Thumb [PR27284] Reverse the ownership between DICompileUnit and DISubprogram. 2016-04-15 15:57:41 +00:00
Thumb2 ARM: use r7 as the frame-pointer on all MachO targets. 2016-04-11 22:27:40 +00:00
WebAssembly [WebAssembly] Move register stackification and coloring to a late phase. 2016-05-10 04:24:02 +00:00
WinEH [PR27284] Reverse the ownership between DICompileUnit and DISubprogram. 2016-04-15 15:57:41 +00:00
X86 [X86][AVX512] Added another masked shuffle combine from load test 2016-05-10 16:55:20 +00:00
XCore [PR27284] Reverse the ownership between DICompileUnit and DISubprogram. 2016-04-15 15:57:41 +00:00