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c64ea03044
When targetting MIPS64R6 some of the patterns for select were guarded by a broken predicate. The predicate was supposed to test if a constant value could fit in a 16 bit zero-extended field. Instead the value was tested to fit in a 16 bit sign-extended field. For negative constants of native word width this resulted in wrong code generation. Reviewers: vkalintiris, dsanders Differential Review: http://reviews.llvm.org/D19378 llvm-svn: 267151
213 lines
7.1 KiB
LLVM
213 lines
7.1 KiB
LLVM
; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=M2 -check-prefix=M2-M3
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; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=CMOV \
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; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R1
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; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=CMOV \
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; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
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; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=CMOV \
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; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
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; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=CMOV \
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; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
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; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-32
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; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=M3 -check-prefix=M2-M3
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; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
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; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
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; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
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; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
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; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
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; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-64
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define signext i1 @tst_select_i1_i1(i1 signext %s,
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i1 signext %x, i1 signext %y) {
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entry:
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; ALL-LABEL: tst_select_i1_i1:
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; M2-M3: andi $[[T0:[0-9]+]], $4, 1
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; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
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; M2-M3: nop
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; M2-M3: move $5, $6
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; M2-M3: $[[BB0]]:
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; M2-M3: jr $ra
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; M2-M3: move $2, $5
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; CMOV: andi $[[T0:[0-9]+]], $4, 1
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; CMOV: movn $6, $5, $[[T0]]
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; CMOV: move $2, $6
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; SEL: andi $[[T0:[0-9]+]], $4, 1
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; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
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; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]]
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; SEL: or $2, $[[T2]], $[[T1]]
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%r = select i1 %s, i1 %x, i1 %y
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ret i1 %r
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}
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define signext i8 @tst_select_i1_i8(i1 signext %s,
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i8 signext %x, i8 signext %y) {
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entry:
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; ALL-LABEL: tst_select_i1_i8:
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; M2-M3: andi $[[T0:[0-9]+]], $4, 1
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; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
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; M2-M3: nop
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; M2-M3: move $5, $6
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; M2-M3: $[[BB0]]:
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; M2-M3: jr $ra
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; M2-M3: move $2, $5
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; CMOV: andi $[[T0:[0-9]+]], $4, 1
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; CMOV: movn $6, $5, $[[T0]]
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; CMOV: move $2, $6
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; SEL: andi $[[T0:[0-9]+]], $4, 1
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; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
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; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]]
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; SEL: or $2, $[[T2]], $[[T1]]
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%r = select i1 %s, i8 %x, i8 %y
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ret i8 %r
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}
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define signext i32 @tst_select_i1_i32(i1 signext %s,
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i32 signext %x, i32 signext %y) {
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entry:
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; ALL-LABEL: tst_select_i1_i32:
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; M2-M3: andi $[[T0:[0-9]+]], $4, 1
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; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
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; M2-M3: nop
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; M2-M3: move $5, $6
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; M2-M3: $[[BB0]]:
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; M2-M3: jr $ra
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; M2-M3: move $2, $5
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; CMOV: andi $[[T0:[0-9]+]], $4, 1
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; CMOV: movn $6, $5, $[[T0]]
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; CMOV: move $2, $6
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; SEL: andi $[[T0:[0-9]+]], $4, 1
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; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
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; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]]
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; SEL: or $2, $[[T2]], $[[T1]]
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%r = select i1 %s, i32 %x, i32 %y
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ret i32 %r
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}
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define signext i64 @tst_select_i1_i64(i1 signext %s,
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i64 signext %x, i64 signext %y) {
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entry:
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; ALL-LABEL: tst_select_i1_i64:
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; M2: andi $[[T0:[0-9]+]], $4, 1
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; M2: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
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; M2: nop
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; M2: lw $[[T1:[0-9]+]], 16($sp)
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; M2: $[[BB0]]:
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; FIXME: This branch is redundant
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; M2: bnez $[[T0]], $[[BB1:BB[0-9_]+]]
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; M2: nop
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; M2: lw $[[T2:[0-9]+]], 20($sp)
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; M2: $[[BB1]]:
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; M2: move $2, $[[T1]]
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; M2: jr $ra
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; M2: move $3, $[[T2]]
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; CMOV-32: andi $[[T0:[0-9]+]], $4, 1
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; CMOV-32: lw $2, 16($sp)
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; CMOV-32: movn $2, $6, $[[T0]]
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; CMOV-32: lw $3, 20($sp)
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; CMOV-32: movn $3, $7, $[[T0]]
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; SEL-32: andi $[[T0:[0-9]+]], $4, 1
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; SEL-32: selnez $[[T1:[0-9]+]], $6, $[[T0]]
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; SEL-32: lw $[[T2:[0-9]+]], 16($sp)
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; SEL-32: seleqz $[[T3:[0-9]+]], $[[T2]], $[[T0]]
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; SEL-32: or $2, $[[T1]], $[[T3]]
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; SEL-32: selnez $[[T4:[0-9]+]], $7, $[[T0]]
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; SEL-32: lw $[[T5:[0-9]+]], 20($sp)
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; SEL-32: seleqz $[[T6:[0-9]+]], $[[T5]], $[[T0]]
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; SEL-32: or $3, $[[T4]], $[[T6]]
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; M3: andi $[[T0:[0-9]+]], $4, 1
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; M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
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; M3: nop
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; M3: move $5, $6
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; M3: $[[BB0]]:
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; M3: jr $ra
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; M3: move $2, $5
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; CMOV-64: andi $[[T0:[0-9]+]], $4, 1
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; CMOV-64: movn $6, $5, $[[T0]]
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; CMOV-64: move $2, $6
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; SEL-64: andi $[[T0:[0-9]+]], $4, 1
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; FIXME: This shift is redundant
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; SEL-64: sll $[[T0]], $[[T0]], 0
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; SEL-64: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
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; SEL-64: selnez $[[T0]], $5, $[[T0]]
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; SEL-64: or $2, $[[T0]], $[[T1]]
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%r = select i1 %s, i64 %x, i64 %y
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ret i64 %r
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}
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define i8* @tst_select_word_cst(i8* %a, i8* %b) {
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; ALL-LABEL: tst_select_word_cst:
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; M2: addiu $1, $zero, -1
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; M2: xor $1, $5, $1
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; M2: sltu $1, $zero, $1
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; M2: bnez $1, $[[BB0:BB[0-9_]+]]
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; M2: addiu $2, $zero, 0
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; M2: move $2, $4
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; M2: $[[BB0]]:
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; M2: jr $ra
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; M3: daddiu $1, $zero, -1
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; M3: xor $1, $5, $1
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; M3: sltu $1, $zero, $1
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; M3: bnez $1, $[[BB0:BB[0-9_]+]]
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; M3: daddiu $2, $zero, 0
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; M3: move $2, $4
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; M3: $[[BB0]]:
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; M3: jr $ra
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; CMOV-32: addiu $1, $zero, -1
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; CMOV-32: xor $1, $5, $1
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; CMOV-32: movn $4, $zero, $1
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; CMOV-32: jr $ra
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; CMOV-32: move $2, $4
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; SEL-32: addiu $1, $zero, -1
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; SEL-32: xor $1, $5, $1
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; SEL-32: sltu $1, $zero, $1
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; SEL-32: jr $ra
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; SEL-32: seleqz $2, $4, $1
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; CMOV-64: daddiu $1, $zero, -1
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; CMOV-64: xor $1, $5, $1
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; CMOV-64: movn $4, $zero, $1
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; CMOV-64: move $2, $4
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; SEL-64: daddiu $1, $zero, -1
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; SEL-64: xor $1, $5, $1
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; SEL-64: sltu $1, $zero, $1
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; FIXME: This shift is redundant.
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; SEL-64: sll $1, $1, 0
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; SEL-64: seleqz $2, $4, $1
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%cmp = icmp eq i8* %b, inttoptr (i64 -1 to i8*)
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%r = select i1 %cmp, i8* %a, i8* null
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ret i8* %r
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}
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