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272d4887f8
So far, we do not yet support any instruction specific to zEC12. Most of the facilities added with zEC12 are indeed not very useful to compiler code generation, but there is one exception: the miscellaneous-extensions facility provides the RISBGN instruction, which is a variant of RISBG that does not set the condition code. Add support for this facility, MC support for RISBGN, and CodeGen support for prefering RISBGN over RISBG on zEC12, unless we can actually make use of the condition code set by RISBG. llvm-svn: 233690
31 lines
740 B
LLVM
31 lines
740 B
LLVM
; Test use of RISBG vs RISBGN on zEC12.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 | FileCheck %s
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; On zEC12, we generally prefer RISBGN.
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define i64 @f1(i64 %a, i64 %b) {
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; CHECK-LABEL: f1:
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; CHECK: risbgn %r2, %r3, 60, 62, 0
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; CHECK: br %r14
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%anda = and i64 %a, -15
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%andb = and i64 %b, 14
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%or = or i64 %anda, %andb
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ret i64 %or
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}
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; But we may fall back to RISBG if we can use the condition code.
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define i64 @f2(i64 %a, i64 %b, i32* %c) {
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; CHECK-LABEL: f2:
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; CHECK: risbg %r2, %r3, 60, 62, 0
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; CHECK-NEXT: ipm
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; CHECK: br %r14
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%anda = and i64 %a, -15
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%andb = and i64 %b, 14
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%or = or i64 %anda, %andb
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%cmp = icmp sgt i64 %or, 0
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%conv = zext i1 %cmp to i32
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store i32 %conv, i32* %c, align 4
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ret i64 %or
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}
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