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The z13 vector facility includes some instructions that operate only on the high f64 in a v2f64, effectively extending the FP register set from 16 to 32 registers. It's still better to use the old instructions if the operands happen to fit though, since the older instructions have a shorter encoding. Based on a patch by Richard Sandiford. llvm-svn: 236524
84 lines
2.6 KiB
LLVM
84 lines
2.6 KiB
LLVM
; Test vector division. There is no native integer support for this,
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; so the integer cases are really a test of the operation legalization code.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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; Test a v16i8 division.
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define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
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; CHECK-LABEL: f1:
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; CHECK: vlvgp [[REG:%v[0-9]+]],
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; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 0
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; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 1
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; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 2
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; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 3
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; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 4
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; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 5
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; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 6
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; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 8
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; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 9
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; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 10
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; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 11
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; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 12
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; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 13
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; CHECK-DAG: vlvgb [[REG]], {{%r[0-5]}}, 14
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; CHECK: br %r14
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%ret = sdiv <16 x i8> %val1, %val2
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ret <16 x i8> %ret
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}
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; Test a v8i16 division.
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define <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
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; CHECK-LABEL: f2:
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; CHECK: vlvgp [[REG:%v[0-9]+]],
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; CHECK-DAG: vlvgh [[REG]], {{%r[0-5]}}, 0
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; CHECK-DAG: vlvgh [[REG]], {{%r[0-5]}}, 1
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; CHECK-DAG: vlvgh [[REG]], {{%r[0-5]}}, 2
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; CHECK-DAG: vlvgh [[REG]], {{%r[0-5]}}, 4
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; CHECK-DAG: vlvgh [[REG]], {{%r[0-5]}}, 5
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; CHECK-DAG: vlvgh [[REG]], {{%r[0-5]}}, 6
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; CHECK: br %r14
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%ret = sdiv <8 x i16> %val1, %val2
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ret <8 x i16> %ret
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}
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; Test a v4i32 division.
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define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
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; CHECK-LABEL: f3:
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; CHECK: vlvgp [[REG:%v[0-9]+]],
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; CHECK-DAG: vlvgf [[REG]], {{%r[0-5]}}, 0
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; CHECK-DAG: vlvgf [[REG]], {{%r[0-5]}}, 2
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; CHECK: br %r14
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%ret = sdiv <4 x i32> %val1, %val2
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ret <4 x i32> %ret
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}
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; Test a v2i64 division.
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define <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
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; CHECK-LABEL: f4:
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; CHECK: vlvgp %v24,
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; CHECK: br %r14
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%ret = sdiv <2 x i64> %val1, %val2
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ret <2 x i64> %ret
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}
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; Test a v2f64 division.
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define <2 x double> @f5(<2 x double> %dummy, <2 x double> %val1,
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<2 x double> %val2) {
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; CHECK-LABEL: f5:
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; CHECK: vfddb %v24, %v26, %v28
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; CHECK: br %r14
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%ret = fdiv <2 x double> %val1, %val2
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ret <2 x double> %ret
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}
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; Test an f64 division that uses vector registers.
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define double @f6(<2 x double> %val1, <2 x double> %val2) {
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; CHECK-LABEL: f6:
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; CHECK: wfddb %f0, %v24, %v26
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; CHECK: br %r14
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%scalar1 = extractelement <2 x double> %val1, i32 0
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%scalar2 = extractelement <2 x double> %val2, i32 0
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%ret = fdiv double %scalar1, %scalar2
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ret double %ret
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}
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