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cd73ce3566
This patch splits backend features currently hidden behind architecture versions. For example, currently the only way to activate complex numbers extension is targeting an v8.3 architecture, where after the patch this extension can be added separately. This refactoring is required by the new command lines proposal: http://lists.llvm.org/pipermail/llvm-dev/2018-September/126346.html Reviewers: DavidSpickett, olista01, t.p.northover Subscribers: kristof.beyls, bryanpkc, javed.absar, pbarrio Differential revision: https://reviews.llvm.org/D54633 -- It was reverted in rL348249 due a build bot failure in one of the regression tests: http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/14386 The problem seems to be that FileCheck behaves different in windows and linux. This new patch splits the test file in multiple, and does more exact pattern matching attempting to circumvent the issue. llvm-svn: 348493
58 lines
2.1 KiB
ArmAsm
58 lines
2.1 KiB
ArmAsm
// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a -o - 2>&1 %s | \
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// RUN: FileCheck %s
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// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+tracev8.4 -o - 2>&1 %s | \
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// RUN: FileCheck %s
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// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.4a -o - %s 2>&1 | \
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// RUN: FileCheck %s --check-prefix=CHECK-ERROR
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// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a,-tracev8.4 -o - %s 2>&1 | \
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// RUN: FileCheck %s --check-prefixes NOFEATURE,CHECK-ERROR
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//------------------------------------------------------------------------------
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// ARMV8.4-A Debug, Trace and PMU Extensions
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//------------------------------------------------------------------------------
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msr TRFCR_EL1, x0
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msr TRFCR_EL2, x0
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msr TRFCR_EL12, x0
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mrs x0, TRFCR_EL1
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mrs x0, TRFCR_EL2
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mrs x0, TRFCR_EL12
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tsb csync
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//CHECK: msr TRFCR_EL1, x0 // encoding: [0x20,0x12,0x18,0xd5]
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//CHECK: msr TRFCR_EL2, x0 // encoding: [0x20,0x12,0x1c,0xd5]
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//CHECK: msr TRFCR_EL12, x0 // encoding: [0x20,0x12,0x1d,0xd5]
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//CHECK: mrs x0, TRFCR_EL1 // encoding: [0x20,0x12,0x38,0xd5]
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//CHECK: mrs x0, TRFCR_EL2 // encoding: [0x20,0x12,0x3c,0xd5]
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//CHECK: mrs x0, TRFCR_EL12 // encoding: [0x20,0x12,0x3d,0xd5]
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//CHECK: tsb csync // encoding: [0x5f,0x22,0x03,0xd5]
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//CHECK-ERROR: error: expected writable system register or pstate
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//CHECK-ERROR: msr TRFCR_EL1, x0
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//CHECK-ERROR: ^
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//CHECK-ERROR: error: expected writable system register or pstate
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//CHECK-ERROR: msr TRFCR_EL2, x0
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//CHECK-ERROR: ^
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//CHECK-ERROR: error: expected writable system register or pstate
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//CHECK-ERROR: msr TRFCR_EL12, x0
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//CHECK-ERROR: ^
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//CHECK-ERROR: error: expected readable system register
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//CHECK-ERROR: mrs x0, TRFCR_EL1
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//CHECK-ERROR: ^
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//CHECK-ERROR: error: expected readable system register
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//CHECK-ERROR: mrs x0, TRFCR_EL2
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//CHECK-ERROR: ^
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//CHECK-ERROR: error: expected readable system register
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//CHECK-ERROR: mrs x0, TRFCR_EL12
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//CHECK-ERROR: ^
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//CHECK-ERROR: error: instruction requires: tracev8.4
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