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llvm-mirror/test/MC/AArch64
Momchil Velikov faa6fb3cc4 [AArch64] Predictably disassemble system registers with the same encoding
The registers TRCEXTINSELR and TRCEXTINSELR0 are distinct registers,
defined by separate extension specifications (ETM and ETE,
respectively), yet they use the same encoding in MSR/MRS.

When performing a system register lookup by encoding, we would
essentially return a random one, depending on the number, relative
position in the TableGen file, whether the TableGen records for system
registers are named or not, and, if they are named, depending on
record (not register!) name as well.

This patch works around the issue by explictly checking for the
TRCEXTINSELR/TRCEXTINSELR0 encoding and always returning TRCEXTINSELR.

Differential Revision: https://reviews.llvm.org/D74074
2020-02-07 12:19:57 +00:00
..
SVE [AArch64][SVE] Allow explicit size specifier for predicate operand 2019-07-25 13:56:04 +00:00
SVE2 [AArch64][SVE2] Rename bitperm feature to sve2-bitperm 2019-07-26 15:57:50 +00:00
adr-diagnostics.s [MC] Delete unnecessary diagnostic: "No relocation available to represent this relative expression" 2019-08-19 07:59:35 +00:00
adr.s [llvm-objdump] Print relocation addends in hexadecimal 2019-11-19 12:27:18 +00:00
adrp-annotation.s
adrp-relocation2.s
adrp-relocation.s
alias-addsubimm.s
alias-logicalimm.s
arm32-elf-relocs.s [llvm-objdump] Print relocation addends in hexadecimal 2019-11-19 12:27:18 +00:00
arm64_32-compact-unwind.s AArch64: support arm64_32, an ILP32 slice for watchOS. 2019-09-12 10:22:23 +00:00
arm64-adr.s
arm64-advsimd.s
arm64-aliases.s
arm64-arithmetic-encoding.s
arm64-arm64-fixup.s
arm64-basic-a64-instructions.s
arm64-be-datalayout.s
arm64-bitfield-encoding.s
arm64-branch-encoding.s
arm64-compact-unwind-fallback.s
arm64-condbr-without-dots.s
arm64-crypto.s
arm64-diagno-predicate.s
arm64-diags.s
arm64-directive_loh.s [NFC] Fix trivial typos in comments 2020-01-06 10:50:26 +00:00
arm64-elf-reloc-condbr.s
arm64-elf-relocs.s [llvm-objdump] Print relocation addends in hexadecimal 2019-11-19 12:27:18 +00:00
arm64-fp-encoding-error.s
arm64-fp-encoding.s
arm64-ilp32.s
arm64-large-relocs.s MC: AArch64: Add support for prel_g* relocation specifiers. 2019-07-18 16:54:33 +00:00
arm64-leaf-compact-unwind.s
arm64-logical-encoding.s
arm64-mapping-across-sections.s
arm64-mapping-within-section.s
arm64-memory.s
arm64-no-section.ll
arm64-nv-cond.s
arm64-optional-hash.s
arm64-separator.s
arm64-simd-ldst.s
arm64-small-data-fixups.s
arm64-spsel-sysreg.s
arm64-system-encoding.s
arm64-target-specific-sysreg.s
arm64-tls-modifiers-darwin.s
arm64-tls-relocs.s
arm64-v128_lo-diagnostics.s
arm64-variable-exprs.s
arm64-vector-lists.s
arm64-verbose-vector-case.s
arm64v8.1-diagno-predicate.s
armv8.1a-atomic.s
armv8.1a-lor.s
armv8.1a-lse.s
armv8.1a-pan.s
armv8.1a-rdma.s
armv8.1a-vhe.s
armv8.2a-at.s
armv8.2a-bfc.s [AArch64InstPrinter] prefer bfi to bfc for < armv8.2-a 2019-10-03 20:10:02 +00:00
armv8.2a-crypto-apple.s AArch64: support the Apple NEON syntax for v8.2 crypto instructions. 2019-11-27 10:54:38 +00:00
armv8.2a-crypto-error.s
armv8.2a-crypto.s
armv8.2a-dotprod-errors.s
armv8.2a-dotprod.s [ARM][AArch64] Support for Cortex-A65 & A65AE, Neoverse E1 & N1 2019-07-25 10:59:45 +00:00
armv8.2a-persistent-memory.s
armv8.2a-statistical-profiling.s [ARM][AArch64] Support for Cortex-A65 & A65AE, Neoverse E1 & N1 2019-07-25 10:59:45 +00:00
armv8.2a-uao.s
armv8.3a-complex_bad.s
armv8.3a-complex_missing.s
armv8.3a-complex_nofp16_bad.s
armv8.3a-complex_nofp16.s
armv8.3a-complex.s
armv8.3a-diagnostics.s
armv8.3a-ID_ISAR6_EL1.s
armv8.3a-js.s
armv8.3a-rcpc.s [ARM][AArch64] Support for Cortex-A65 & A65AE, Neoverse E1 & N1 2019-07-25 10:59:45 +00:00
armv8.3a-signed-pointer.s [AArch64] Emit HINT instead of PAC insns in Armv8.2-A or below 2020-01-13 14:14:48 +00:00
armv8.4a-actmon.s
armv8.4a-dit.s
armv8.4a-flag-error.s
armv8.4a-flag.s
armv8.4a-ldst-error.s
armv8.4a-ldst.s
armv8.4a-mpam.s
armv8.4a-pmu.s [AArch64] Adding support for PMMIR_EL1 register 2019-10-18 12:40:29 +00:00
armv8.4a-ras.s
armv8.4a-tlb.s
armv8.4a-trace-error.s
armv8.4a-trace.s
armv8.4a-virt.s
armv8.4a-vncr.s
armv8.5a-altnzcv.s
armv8.5a-bti-error.s
armv8.5a-bti.s
armv8.5a-frint-error.s
armv8.5a-frint.s
armv8.5a-mte-error.s
armv8.5a-mte.s [AArch64] Update MTE system register encodings 2019-08-21 09:09:56 +00:00
armv8.5a-persistent-memory.s
armv8.5a-predres-error.s
armv8.5a-predres.s
armv8.5a-rand-error.s
armv8.5a-rand.s
armv8.5a-sb.s
armv8.5a-specrestrict.s
armv8.5a-ssbs-error.s
armv8.5a-ssbs.s [ARM][AArch64] Support for Cortex-A65 & A65AE, Neoverse E1 & N1 2019-07-25 10:59:45 +00:00
armv8.5a-xaflag-error.s
armv8a-fpmul-error.s
armv8a-fpmul.s
atomic-acquire-comment.s
basic-a64-diagnostics.s [AArch64,Assembler] Compiler support for ID_MMFR5_EL1 2019-10-16 15:59:06 +00:00
basic-a64-instructions.s [AArch64,Assembler] Compiler support for ID_MMFR5_EL1 2019-10-16 15:59:06 +00:00
basic-pic.s
case-insen-reg-names.s
cfi.s
CheckDataSymbol.s
coff-align.s
coff-basic.ll
coff-debug.ll Migrate function attribute "no-frame-pointer-elim"="false" to "frame-pointer"="none" as cleanups after D56351 2019-12-24 16:27:51 -08:00
coff-function-type-info.ll
coff-gnu.s
coff-relocations.s
cold.s
crc.s
cyclone-movi-bug.s
darwin-reloc-addsubimm.s
directive-arch_extension-negative.s
directive-arch_extension.s
directive-arch-negative.s
directive-arch.s
directive-cpu-err.s
directive-cpu.s
directives-case_insensitive.s [AArch64] Make AArch64 specific assembly directives case insensitive 2020-01-17 16:16:18 +00:00
dot-req-case-insensitive.s
dot-req-diagnostics.s
dot-req.s
elf_osabi_flags.s
elf-extern.s
elf-globaladdress.ll
elf-objdump.s
elf-reloc-addsubimm.s
elf-reloc-ldrlit.s
elf-reloc-ldstunsimm.s
elf-reloc-movw.s
elf-reloc-pcreladdressing.s
elf-reloc-tstb.s
elf-reloc-uncondbrimm.s
error-location-during-layout.s
error-location-ldr-pseudo.s
error-location-post-layout.s
error-location.s [MC] Delete unnecessary diagnostic: "No relocation available to represent this relative expression" 2019-08-19 07:59:35 +00:00
ete-sysregs.s [AArch64] Predictably disassemble system registers with the same encoding 2020-02-07 12:19:57 +00:00
expr-bad-symbol.s
expr-shr.s
fixup-absolute-signed.s
fixup-absolute.s
fixup-out-of-range.s
fullfp16-diagnostics.s
fullfp16-neon-neg.s
gicv3-regs-diagnostics.s
gicv3-regs.s [Target][AArch64] Remove non-existing system registers ICH_VSEIR_EL2 & ICC_SEIEN_EL1 from AArch64 backend 2020-02-07 09:44:41 +00:00
ilp32-diagnostics.s
inline-asm-modifiers.s
inst-directive-diagnostic.s
inst-directive-other.s
inst-directive.s
invalid-instructions-spellcheck.s
ir-to-imgrel.ll
jump-table.s
label-arithmetic-darwin.s
label-arithmetic-diags-darwin.s
label-arithmetic-diags-elf.s
label-arithmetic-elf.s
ldr-pseudo-diagnostics.s
ldr-pseudo-obj-errors.s
ldr-pseudo.s
lit.local.cfg
macho-adrp-missing-reloc.s
macho-adrp-page.s
macro-hex-int.s
mapping-across-sections.s
mapping-within-section.s
neon-2velem.s
neon-3vdiff.s
neon-aba-abd.s
neon-across.s
neon-add-pairwise.s
neon-add-sub-instructions.s
neon-bitwise-instructions.s
neon-compare-instructions.s
neon-crypto.s
neon-diagnostics.s
neon-extract.s
neon-facge-facgt.s
neon-frsqrt-frecp.s
neon-halving-add-sub.s
neon-max-min-pairwise.s
neon-max-min.s
neon-mla-mls-instructions.s
neon-mov.s
neon-mul-div-instructions.s
neon-perm.s
neon-rounding-halving-add.s
neon-rounding-shift.s
neon-saturating-add-sub.s
neon-saturating-rounding-shift.s
neon-saturating-shift.s
neon-scalar-abs.s
neon-scalar-add-sub.s
neon-scalar-by-elem-mla.s
neon-scalar-by-elem-mul.s
neon-scalar-by-elem-saturating-mla.s
neon-scalar-by-elem-saturating-mul.s
neon-scalar-compare.s
neon-scalar-cvt.s
neon-scalar-dup.s
neon-scalar-extract-narrow.s
neon-scalar-fp-compare.s
neon-scalar-mul.s
neon-scalar-neg.s
neon-scalar-recip.s
neon-scalar-reduce-pairwise.s
neon-scalar-rounding-shift.s
neon-scalar-saturating-add-sub.s
neon-scalar-saturating-rounding-shift.s
neon-scalar-saturating-shift.s
neon-scalar-shift-imm.s
neon-scalar-shift.s
neon-shift-left-long.s
neon-shift.s
neon-simd-copy.s
neon-simd-ldst-multi-elem.s
neon-simd-ldst-one-elem.s
neon-simd-misc.s
neon-simd-post-ldst-multi-elem.s
neon-simd-shift.s
neon-sxtl.s
neon-tbl.s
neon-uxtl.s
nofp-crypto-diagnostic.s
noneon-diagnostics.s
optional-hash.s
ras-extension.s
reloc-directive.s
seh.s
shift_extend_op_w_symbol.s
single-slash.s
size-directive.s
speculation-barriers.s
tls-add-shift.s
tls-relocs.s
tme-error.s [AArch64] Add support for Transactional Memory Extension (TME) 2019-07-31 12:52:17 +00:00
tme.s [AArch64] Add support for Transactional Memory Extension (TME) 2019-07-31 12:52:17 +00:00
trace-regs-diagnostics.s
trace-regs.s [AArch64] Predictably disassemble system registers with the same encoding 2020-02-07 12:19:57 +00:00
trbe-sysreg-diag.s [AArch64] Define ETE and TRBE system registers 2019-07-26 09:19:08 +00:00
trbe-sysreg.s [AArch64] Define ETE and TRBE system registers 2019-07-26 09:19:08 +00:00
udf_not.s
udf.s