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0020aa4a64
Whenever an add/sub immediate needs a fixup, we set that immediate field to zero, which is correct, but we also set the shift bits to zero, which is not true for instructions that use lsl #12. This patch makes sure that if lsl #12 was used, it will appear in the encoding of the instruction. Differential Revision: https://reviews.llvm.org/D23930 llvm-svn: 281898
14 lines
509 B
ArmAsm
14 lines
509 B
ArmAsm
// RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj %s -o - | \
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// RUN: llvm-objdump -r -d - | FileCheck -check-prefix=OBJ %s
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// OBJ-LABEL: Disassembly of section .text:
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add x2, x3, #:lo12:some_label
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// OBJ: [[addr:[0-9a-f]+]]: 62 00 00 91 add x2, x3, #0
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// OBJ-NEXT: [[addr]]: R_AARCH64_ADD_ABS_LO12_NC some_label
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add x2, x3, #:lo12:some_label, lsl #12
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// OBJ: [[addr:[0-9a-f]+]]: 62 00 40 91 add x2, x3, #0, lsl #12
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// OBJ-NEXT: [[addr]]: R_AARCH64_ADD_ABS_LO12_NC some_label
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