Tom Stellard 7b93a88a1e Revert "[AArch64][GlobalISel] Legalize bswap <2 x i16>" ... This reverts commit 5cd63e9ec2a385de2682949c0bbe928afaf35c91. https://bugs.llvm.org/show_bug.cgi?id=51707		2021-09-10 21:09:59 -07:00
..
AArch64	Revert "[AArch64][GlobalISel] Legalize bswap <2 x i16>"	2021-09-10 21:09:59 -07:00
AMDGPU	AMDGPU/GlobalISel: Fix selecting G_SEXTLOAD/G_ZEXTLOAD pre-gfx9	2021-07-27 15:56:42 -04:00
ARC
ARM	[ARM][atomicrmw] Fix CMP_SWAP_32 expand assert	2021-08-18 12:14:24 -07:00
AVR	[AVR] Only support sp, r0 and r1 in llvm.read_register	2021-07-24 14:03:27 +02:00
BPF	BPF: avoid NE/EQ loop exit condition	2021-08-06 12:45:53 -07:00
Generic	[PowerPC] Add pwr7 and pwr10 support to IBM MASSV pass on AIX	2021-07-26 23:21:38 +00:00
Hexagon	[Hexagon] Fix resetting dead registers in DBG_VALUE_LISTs	2021-07-27 18:36:28 -05:00
Inputs
Lanai
M68k	[M68k][GloballSel] LegalizerInfo implementation	2021-07-15 13:00:43 -06:00
Mips	Revert [MC][ELF] Emit separate unique sections for different flags	2021-09-10 16:55:29 -07:00
MIR
MSP430
NVPTX	[NVPTX] Add select(cc,binop(),binop()) fast-math tests	2021-07-18 15:30:24 +01:00
PowerPC	Revert "[HardwareLoops] Change order of SCEV expression construction for InitLoopCount."	2021-09-08 20:46:17 -07:00
RISCV	[RISCV] Fix reporting of incorrect commutable operand indices	2021-09-03 15:48:26 -07:00
SPARC
SystemZ	[SystemZ][z/OS] Initial code to generate assembly files on z/OS	2021-07-27 11:29:15 -04:00
Thumb
Thumb2	[SimplifyCFG] performBranchToCommonDestFolding(): require block-closed SSA form for bonus instructions (PR51125)	2021-09-10 09:02:26 -07:00
VE
WebAssembly	[WebAssembly] Fix FastISel of condition in different block (PR51651)	2021-08-31 20:58:25 -07:00
WinCFGuard
WinEH
X86	Revert [MC][ELF] Emit separate unique sections for different flags	2021-09-10 16:55:29 -07:00
XCore