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196e7f3138
Replace individual operands GLC, SLC, and DLC with a single cache_policy bitmask operand. This will reduce the number of operands in MIR and I hope the amount of code. These operands are mostly 0 anyway. Additional advantage that parser will accept these flags in any order unlike now. Differential Revision: https://reviews.llvm.org/D96469
28 lines
882 B
YAML
28 lines
882 B
YAML
# RUN: llc -o - %s -march=amdgcn -mcpu=fiji -run-pass=machine-cp -verify-machineinstrs | FileCheck -check-prefix=GCN %s
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# GCN-LABEL: dead_copy
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# GCN: bb.0
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# GCN-NOT: dead $vgpr5 = COPY undef $vgpr11, implicit $exec
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# GCN: $vgpr5 = COPY $vgpr11, implicit $exec
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---
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name: dead_copy
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body: |
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bb.0:
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liveins: $vgpr11, $sgpr0, $sgpr1, $vgpr6, $vgpr7, $vgpr4
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dead $vgpr5 = COPY undef $vgpr11, implicit $exec
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$vgpr5 = COPY $vgpr11, implicit $exec
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$sgpr14 = S_ADD_U32 $sgpr0, target-flags(amdgpu-gotprel) 1136, implicit-def $scc
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$sgpr15 = S_ADDC_U32 $sgpr1, target-flags(amdgpu-gotprel32-lo) 0, implicit-def dead $scc, implicit $scc
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$vgpr10 = COPY killed $sgpr14, implicit $exec
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$vgpr11 = COPY killed $sgpr15, implicit $exec
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FLAT_STORE_DWORDX4 $vgpr10_vgpr11, $vgpr4_vgpr5_vgpr6_vgpr7, 0, 0, implicit $exec, implicit $flat_scr
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...
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