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73bc91a5e6
This reverts commit bda6e5bee04c75b1f1332b4fd1ac4e8ef6c3c247. See https://lab.llvm.org/buildbot/#/builders/109/builds/15424 for instance
76 lines
2.6 KiB
LLVM
76 lines
2.6 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s -check-prefix=SI -check-prefix=FUNC
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s -check-prefix=SI -check-prefix=FUNC
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s -check-prefix=R600 -check-prefix=FUNC
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; FUNC-LABEL: {{^}}fadd_f32:
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; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].W
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; SI: v_add_f32
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define amdgpu_kernel void @fadd_f32(float addrspace(1)* %out, float %a, float %b) #0 {
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%add = fadd float %a, %b
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store float %add, float addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}fadd_v2f32:
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; R600-DAG: ADD {{\** *}}T{{[0-9]\.[XYZW]}}, KC0[3].X, KC0[3].Z
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; R600-DAG: ADD {{\** *}}T{{[0-9]\.[XYZW]}}, KC0[2].W, KC0[3].Y
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; SI: v_add_f32
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; SI: v_add_f32
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define amdgpu_kernel void @fadd_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) #0 {
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%add = fadd <2 x float> %a, %b
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store <2 x float> %add, <2 x float> addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}fadd_v4f32:
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; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; SI: v_add_f32
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; SI: v_add_f32
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; SI: v_add_f32
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; SI: v_add_f32
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define amdgpu_kernel void @fadd_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) #0 {
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%b_ptr = getelementptr <4 x float>, <4 x float> addrspace(1)* %in, i32 1
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%a = load <4 x float>, <4 x float> addrspace(1)* %in, align 16
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%b = load <4 x float>, <4 x float> addrspace(1)* %b_ptr, align 16
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%result = fadd <4 x float> %a, %b
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store <4 x float> %result, <4 x float> addrspace(1)* %out, align 16
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ret void
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}
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; FUNC-LABEL: {{^}}fadd_v8f32:
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; R600: ADD
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; R600: ADD
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; R600: ADD
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; R600: ADD
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; R600: ADD
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; R600: ADD
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; R600: ADD
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; R600: ADD
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; SI: v_add_f32
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; SI: v_add_f32
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; SI: v_add_f32
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; SI: v_add_f32
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; SI: v_add_f32
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; SI: v_add_f32
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; SI: v_add_f32
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; SI: v_add_f32
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define amdgpu_kernel void @fadd_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %a, <8 x float> %b) #0 {
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%add = fadd <8 x float> %a, %b
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store <8 x float> %add, <8 x float> addrspace(1)* %out, align 32
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ret void
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}
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; FUNC-LABEL: {{^}}fadd_0_nsz_attr_f32:
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; SI-NOT: v_add_f32
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define amdgpu_kernel void @fadd_0_nsz_attr_f32(float addrspace(1)* %out, float %a) #1 {
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%add = fadd nsz float %a, 0.0
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store float %add, float addrspace(1)* %out, align 4
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ret void
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind "no-signed-zeros-fp-math"="true" }
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