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a70016c8d5
Add the scratch wave offset to the scratch buffer descriptor (SRSrc) in the entry function prologue. This allows us to removes the scratch wave offset register from the calling convention ABI. As part of this change, allow the use of an inline constant zero for the SOffset of MUBUF instructions accessing the stack in entry functions when a frame pointer is not requested/required. Entry functions with calls still need to set up the calling convention ABI stack pointer register, and reference it in order to address arguments of called functions. The ABI stack pointer register remains unswizzled, but is now wave-relative instead of queue-relative. Non-entry functions also use an inline constant zero SOffset for wave-relative scratch access, but continue to use the stack and frame pointers as before. When the stack or frame pointer is converted to a swizzled offset it is now scaled directly, as the scratch wave offset no longer needs to be subtracted first. Update llvm/docs/AMDGPUUsage.rst to reflect these changes to the calling convention. Tags: #llvm Differential Revision: https://reviews.llvm.org/D75138
125 lines
5.1 KiB
LLVM
125 lines
5.1 KiB
LLVM
; RUN: llc -amdgpu-scalarize-global-loads=false -verify-machineinstrs -march=amdgcn < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -verify-machineinstrs -march=amdgcn -mcpu=tonga < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
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; When a frame index offset is more than 12-bits, make sure we don't store
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; it in mubuf's offset field.
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; Also, make sure we use the same register for storing the scratch buffer addresss
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; for both stores. This register is allocated by the register scavenger, so we
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; should be able to reuse the same regiser for each scratch buffer access.
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; GCN-LABEL: {{^}}legal_offset_fi:
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; GCN: buffer_store_dword v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:4{{$}}
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; GCN: v_mov_b32_e32 [[OFFSET:v[0-9]+]], 0x8004
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; GCN: buffer_store_dword v{{[0-9]+}}, [[OFFSET]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offen{{$}}
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define amdgpu_kernel void @legal_offset_fi(i32 addrspace(1)* %out, i32 %cond, i32 %if_offset, i32 %else_offset) {
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entry:
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%scratch0 = alloca [8192 x i32], addrspace(5)
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%scratch1 = alloca [8192 x i32], addrspace(5)
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%scratchptr0 = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %scratch0, i32 0, i32 0
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store i32 1, i32 addrspace(5)* %scratchptr0
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%scratchptr1 = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %scratch1, i32 0, i32 0
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store i32 2, i32 addrspace(5)* %scratchptr1
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%cmp = icmp eq i32 %cond, 0
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br i1 %cmp, label %if, label %else
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if:
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%if_ptr = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %scratch0, i32 0, i32 %if_offset
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%if_value = load i32, i32 addrspace(5)* %if_ptr
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br label %done
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else:
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%else_ptr = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %scratch1, i32 0, i32 %else_offset
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%else_value = load i32, i32 addrspace(5)* %else_ptr
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br label %done
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done:
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%value = phi i32 [%if_value, %if], [%else_value, %else]
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store i32 %value, i32 addrspace(1)* %out
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ret void
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ret void
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}
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; GCN-LABEL: {{^}}legal_offset_fi_offset:
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; GCN-DAG: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offen{{$}}
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; This constant isn't folded, because it has multiple uses.
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; GCN-DAG: v_mov_b32_e32 [[K8000:v[0-9]+]], 0x8004
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; GCN-DAG: v_add_{{[iu]}}32_e32 [[OFFSET:v[0-9]+]], vcc, [[K8000]]
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; GCN: buffer_store_dword v{{[0-9]+}}, [[OFFSET]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offen{{$}}
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define amdgpu_kernel void @legal_offset_fi_offset(i32 addrspace(1)* %out, i32 %cond, i32 addrspace(1)* %offsets, i32 %if_offset, i32 %else_offset) {
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entry:
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%scratch0 = alloca [8192 x i32], addrspace(5)
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%scratch1 = alloca [8192 x i32], addrspace(5)
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%offset0 = load i32, i32 addrspace(1)* %offsets
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%scratchptr0 = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %scratch0, i32 0, i32 %offset0
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store i32 %offset0, i32 addrspace(5)* %scratchptr0
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%offsetptr1 = getelementptr i32, i32 addrspace(1)* %offsets, i32 1
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%offset1 = load i32, i32 addrspace(1)* %offsetptr1
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%scratchptr1 = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %scratch1, i32 0, i32 %offset1
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store i32 %offset1, i32 addrspace(5)* %scratchptr1
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%cmp = icmp eq i32 %cond, 0
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br i1 %cmp, label %if, label %else
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if:
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%if_ptr = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %scratch0, i32 0, i32 %if_offset
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%if_value = load i32, i32 addrspace(5)* %if_ptr
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br label %done
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else:
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%else_ptr = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %scratch1, i32 0, i32 %else_offset
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%else_value = load i32, i32 addrspace(5)* %else_ptr
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br label %done
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done:
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%value = phi i32 [%if_value, %if], [%else_value, %else]
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store i32 %value, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}neg_vaddr_offset_inbounds:
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; GCN: v_add_{{[iu]}}32_e32 [[ADD:v[0-9]+]], vcc, 16, v{{[0-9]+}}
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; GCN: buffer_store_dword v{{[0-9]+}}, [[ADD]], s[{{[0-9]+:[0-9]+}}], 0 offen{{$}}
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define amdgpu_kernel void @neg_vaddr_offset_inbounds(i32 %offset) {
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entry:
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%array = alloca [8192 x i32], addrspace(5)
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%ptr_offset = add i32 %offset, 4
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%ptr = getelementptr inbounds [8192 x i32], [8192 x i32] addrspace(5)* %array, i32 0, i32 %ptr_offset
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store i32 0, i32 addrspace(5)* %ptr
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ret void
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}
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; GCN-LABEL: {{^}}neg_vaddr_offset:
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; GCN: v_add_{{[iu]}}32_e32 [[ADD:v[0-9]+]], vcc, 16, v{{[0-9]+}}
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; GCN: buffer_store_dword v{{[0-9]+}}, [[ADD]], s[{{[0-9]+:[0-9]+}}], 0 offen{{$}}
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define amdgpu_kernel void @neg_vaddr_offset(i32 %offset) {
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entry:
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%array = alloca [8192 x i32], addrspace(5)
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%ptr_offset = add i32 %offset, 4
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%ptr = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %array, i32 0, i32 %ptr_offset
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store i32 0, i32 addrspace(5)* %ptr
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ret void
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}
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; GCN-LABEL: {{^}}pos_vaddr_offset:
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; GCN: buffer_store_dword v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], 0 offset:20
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define amdgpu_kernel void @pos_vaddr_offset(i32 addrspace(1)* %out, i32 %offset) {
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entry:
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%array = alloca [8192 x i32], addrspace(5)
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%ptr = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %array, i32 0, i32 4
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store i32 0, i32 addrspace(5)* %ptr
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%load_ptr = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %array, i32 0, i32 %offset
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%val = load i32, i32 addrspace(5)* %load_ptr
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store i32 %val, i32 addrspace(1)* %out
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ret void
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}
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