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cb35142c34
Fix 64-bit copy to SCC by restricting the pattern resulting in such a copy to subtargets supporting 64-bit scalar compare, and mapping the copy to S_CMP_LG_U64. Before introducing the S_CSELECT pattern with explicit SCC (0045786f146e78afee49eee053dc29ebc842fee1), there was no need for handling 64-bit copy to SCC ($scc = COPY sreg_64). The proposed handling to read only the low bits was however based on a false premise that it is only one bit that matters, while in fact the copy source might be a vector of booleans and all bits need to be considered. The practical problem of mapping the 64-bit copy to SCC is that the natural instruction to use (S_CMP_LG_U64) is not available on old hardware. Fix it by restricting the problematic pattern to subtargets supporting the instruction (hasScalarCompareEq64). Differential Revision: https://reviews.llvm.org/D85207
128 lines
5.2 KiB
LLVM
128 lines
5.2 KiB
LLVM
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=cypress < %s | FileCheck -enable-var-scope -check-prefix=EG %s
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declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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define amdgpu_kernel void @trunc_i64_to_i32_store(i32 addrspace(1)* %out, [8 x i32], i64 %in) {
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; GCN-LABEL: {{^}}trunc_i64_to_i32_store:
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; GCN: s_load_dword [[SLOAD:s[0-9]+]], s[0:1],
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; GCN: v_mov_b32_e32 [[VLOAD:v[0-9]+]], [[SLOAD]]
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; SI: buffer_store_dword [[VLOAD]]
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; VI: flat_store_dword v[{{[0-9:]+}}], [[VLOAD]]
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; EG-LABEL: {{^}}trunc_i64_to_i32_store:
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; EG: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
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; EG: LSHR
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; EG-NEXT: 2(
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%result = trunc i64 %in to i32 store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}trunc_load_shl_i64:
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; GCN-DAG: s_load_dwordx2
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; GCN-DAG: s_load_dword [[SREG:s[0-9]+]],
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; GCN: s_lshl_b32 [[SHL:s[0-9]+]], [[SREG]], 2
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; GCN: v_mov_b32_e32 [[VSHL:v[0-9]+]], [[SHL]]
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; SI: buffer_store_dword [[VSHL]]
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; VI: flat_store_dword v[{{[0-9:]+}}], [[VSHL]]
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define amdgpu_kernel void @trunc_load_shl_i64(i32 addrspace(1)* %out, [8 x i32], i64 %a) {
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%b = shl i64 %a, 2
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%result = trunc i64 %b to i32
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}trunc_shl_i64:
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; SI: s_load_dwordx2 s{{\[}}[[LO_SREG:[0-9]+]]:{{[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xd
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; VI: s_load_dwordx2 s{{\[}}[[LO_SREG:[0-9]+]]:{{[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x34
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; GCN: s_lshl_b64 s{{\[}}[[LO_SHL:[0-9]+]]:{{[0-9]+\]}}, s{{\[}}[[LO_SREG]]:{{[0-9]+\]}}, 2
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; GCN: s_add_u32 s[[LO_SREG2:[0-9]+]], s[[LO_SHL]],
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; GCN: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], s[[LO_SREG2]]
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; GCN: s_addc_u32
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; SI: buffer_store_dword v[[LO_VREG]],
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; VI: flat_store_dword v[{{[0-9:]+}}], v[[LO_VREG]]
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; GCN: v_mov_b32_e32
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; GCN: v_mov_b32_e32
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define amdgpu_kernel void @trunc_shl_i64(i64 addrspace(1)* %out2, i32 addrspace(1)* %out, i64 %a) {
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%aa = add i64 %a, 234 ; Prevent shrinking store.
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%b = shl i64 %aa, 2
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%result = trunc i64 %b to i32
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store i32 %result, i32 addrspace(1)* %out, align 4
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store i64 %b, i64 addrspace(1)* %out2, align 8 ; Prevent reducing ops to 32-bits
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ret void
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}
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; GCN-LABEL: {{^}}trunc_i32_to_i1:
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; GCN: v_and_b32_e32 [[VREG:v[0-9]+]], 1, v{{[0-9]+}}
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define amdgpu_kernel void @trunc_i32_to_i1(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) {
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%a = load i32, i32 addrspace(1)* %ptr, align 4
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%trunc = trunc i32 %a to i1
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%result = select i1 %trunc, i32 1, i32 0
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}trunc_i8_to_i1:
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; GCN: v_and_b32_e32 [[VREG:v[0-9]+]], 1, v{{[0-9]+}}
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define amdgpu_kernel void @trunc_i8_to_i1(i8 addrspace(1)* %out, i8 addrspace(1)* %ptr) {
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%a = load i8, i8 addrspace(1)* %ptr, align 4
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%trunc = trunc i8 %a to i1
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%result = select i1 %trunc, i8 1, i8 0
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store i8 %result, i8 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}sgpr_trunc_i16_to_i1:
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; GCN: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 1
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define amdgpu_kernel void @sgpr_trunc_i16_to_i1(i16 addrspace(1)* %out, i16 %a) {
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%trunc = trunc i16 %a to i1
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%result = select i1 %trunc, i16 1, i16 0
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store i16 %result, i16 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}sgpr_trunc_i32_to_i1:
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; GCN: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 1
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define amdgpu_kernel void @sgpr_trunc_i32_to_i1(i32 addrspace(1)* %out, i32 %a) {
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%trunc = trunc i32 %a to i1
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%result = select i1 %trunc, i32 1, i32 0
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}s_trunc_i64_to_i1:
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; SI: s_load_dwordx2 s{{\[}}[[SLO:[0-9]+]]:{{[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0x13
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; VI: s_load_dwordx2 s{{\[}}[[SLO:[0-9]+]]:{{[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0x4c
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; GCN: s_and_b32 [[MASKED:s[0-9]+]], 1, s[[SLO]]
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; GCN: v_cmp_eq_u32_e64 s{{\[}}[[VLO:[0-9]+]]:[[VHI:[0-9]+]]], [[MASKED]], 1{{$}}
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; SI: v_cndmask_b32_e64 {{v[0-9]+}}, -12, 63, s{{\[}}[[VLO]]:[[VHI]]]
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; VI: s_cmp_lg_u64 s{{\[}}[[VLO]]:[[VHI]]], 0
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; VI: s_cselect_b32 {{s[0-9]+}}, 63, -12
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define amdgpu_kernel void @s_trunc_i64_to_i1(i32 addrspace(1)* %out, [8 x i32], i64 %x) {
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%trunc = trunc i64 %x to i1
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%sel = select i1 %trunc, i32 63, i32 -12
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store i32 %sel, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}v_trunc_i64_to_i1:
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; SI: buffer_load_dwordx2 v{{\[}}[[VLO:[0-9]+]]:{{[0-9]+\]}}
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; VI: flat_load_dwordx2 v{{\[}}[[VLO:[0-9]+]]:{{[0-9]+\]}}
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; GCN: v_and_b32_e32 [[MASKED:v[0-9]+]], 1, v[[VLO]]
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; GCN: v_cmp_eq_u32_e32 vcc, 1, [[MASKED]]
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; GCN: v_cndmask_b32_e64 {{v[0-9]+}}, -12, 63, vcc
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define amdgpu_kernel void @v_trunc_i64_to_i1(i32 addrspace(1)* %out, i64 addrspace(1)* %in) {
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%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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%gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
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%out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
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%x = load i64, i64 addrspace(1)* %gep
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%trunc = trunc i64 %x to i1
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%sel = select i1 %trunc, i32 63, i32 -12
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store i32 %sel, i32 addrspace(1)* %out.gep
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ret void
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}
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