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c1aa25f196
This bug was exposed by the rL360395. Differential Revision: https://reviews.llvm.org/D61812 llvm-svn: 360689
24 lines
962 B
LLVM
24 lines
962 B
LLVM
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; This test used to crash
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; GCN-LABEL: {{^}}xor3_i1_const:
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; GCN: s_xor_b64 s[{{[0-9:]+}}], s[{{[0-9:]+}}], -1
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; GCN: s_xor_b64 s[{{[0-9:]+}}], s[{{[0-9:]+}}], -1
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define amdgpu_ps float @xor3_i1_const(float inreg %arg1, i32 inreg %arg2) {
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main_body:
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%tmp26 = fcmp nsz olt float %arg1, 0.000000e+00
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%tmp28 = call nsz float @llvm.amdgcn.interp.p2(float undef, float undef, i32 0, i32 0, i32 %arg2)
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%tmp29 = fcmp nsz olt float %arg1, 5.700000e+01
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%tmp31 = fcmp nsz olt float %tmp28, 0.000000e+00
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%.demorgan = and i1 %tmp26, %tmp29
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%tmp34 = xor i1 %.demorgan, true
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%tmp35 = and i1 %tmp31, %tmp34
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%tmp36 = xor i1 %tmp35, true
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%tmp37 = xor i1 %.demorgan, %tmp36
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%tmp42 = or i1 %tmp37, %tmp35
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%tmp43 = select i1 %tmp42, float 1.000000e+00, float 0.000000e+00
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ret float %tmp43
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}
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declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32)
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