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262321d1ff
This patch lets the llvm tools handle the new HVX target features that
are added by frontend (clang). The target-features are of the form
"hvx-length64b" for 64 Byte HVX mode, "hvx-length128b" for 128 Byte mode HVX.
"hvx-double" is an alias to "hvx-length128b" and is soon will be deprecated.
The hvx version target feature is upgated form "+hvx" to "+hvxv{version_number}.
Eg: "+hvxv62"
For the correct HVX code generation, the user must use the following
target features.
For 64B mode: "+hvxv62" "+hvx-length64b"
For 128B mode: "+hvxv62" "+hvx-length128b"
Clang picks a default length if none is specified. If for some reason,
no hvx-length is specified to llvm, the compilation will bail out.
There is a corresponding clang patch.
Differential Revision: https://reviews.llvm.org/D38851
llvm-svn: 316101
49 lines
2.0 KiB
LLVM
49 lines
2.0 KiB
LLVM
; RUN: llc -march=hexagon < %s | FileCheck %s
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@v0 = global <16 x i32> zeroinitializer, align 64
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@v1 = global <16 x i32> zeroinitializer, align 64
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; CHECK-LABEL: danny:
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; CHECK-NOT: vcombine
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define void @danny() #0 {
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%t0 = load <16 x i32>, <16 x i32>* @v0, align 64
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%t1 = load <16 x i32>, <16 x i32>* @v1, align 64
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%t2 = call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %t0, <16 x i32> %t1)
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%t3 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %t2)
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%t4 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %t2)
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store <16 x i32> %t3, <16 x i32>* @v0, align 64
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store <16 x i32> %t4, <16 x i32>* @v1, align 64
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ret void
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}
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@w0 = global <32 x i32> zeroinitializer, align 128
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@w1 = global <32 x i32> zeroinitializer, align 128
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; CHECK-LABEL: sammy:
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; CHECK-NOT: vcombine
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define void @sammy() #1 {
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%t0 = load <32 x i32>, <32 x i32>* @w0, align 128
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%t1 = load <32 x i32>, <32 x i32>* @w1, align 128
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%t2 = call <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32> %t0, <32 x i32> %t1)
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%t3 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> %t2)
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%t4 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %t2)
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store <32 x i32> %t3, <32 x i32>* @w0, align 128
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store <32 x i32> %t4, <32 x i32>* @w1, align 128
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ret void
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}
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declare <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32>, <16 x i32>) #2
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declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #2
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declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #2
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declare <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32>, <32 x i32>) #3
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declare <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32>) #3
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declare <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32>) #3
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attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
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attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }
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attributes #2 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
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attributes #3 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }
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