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https://github.com/RPCS3/llvm-mirror.git
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c28d8cf19b
This commit removes the artificial types <512 x i1> and <1024 x i1>
from HVX intrinsics, and makes v512i1 and v1024i1 no longer legal on
Hexagon.
It may cause existing bitcode files to become invalid.
* Converting between vector predicates and vector registers must be
done explicitly via vandvrt/vandqrt instructions (their intrinsics),
i.e. (for 64-byte mode):
%Q = call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %V, i32 -1)
%V = call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %Q, i32 -1)
The conversion intrinsics are:
declare <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32)
declare <128 x i1> @llvm.hexagon.V6.vandvrt.128B(<32 x i32>, i32)
declare <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1>, i32)
declare <32 x i32> @llvm.hexagon.V6.vandqrt.128B(<128 x i1>, i32)
They are all pure.
* Vector predicate values cannot be loaded/stored directly. This directly
reflects the architecture restriction. Loading and storing or vector
predicates must be done indirectly via vector registers and explicit
conversions via vandvrt/vandqrt instructions.
205 lines
12 KiB
LLVM
205 lines
12 KiB
LLVM
; RUN: llc -march=hexagon < %s
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; REQUIRES: asserts
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; Test that the register scavenger does not fail because it can't find
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; a spill slot. This occurs the offset for a spilled object is too large
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; and requires another register to compute the location on the stack.
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; Function Attrs: nounwind
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define void @f0(i8* nocapture readonly %a0, i32 %a1, i32 %a2, i8* nocapture readonly %a3, i8* nocapture readonly %a4, i8* nocapture %a5) #0 {
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b0:
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%v0 = tail call <16 x i32> @llvm.hexagon.V6.vshuffb(<16 x i32> zeroinitializer)
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br i1 undef, label %b1, label %b5
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b1: ; preds = %b0
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%v1 = getelementptr inbounds i8, i8* %a3, i32 31
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br label %b2
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b2: ; preds = %b4, %b1
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%v2 = phi <16 x i32>* [ undef, %b1 ], [ %v102, %b4 ]
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%v3 = phi i32 [ %a2, %b1 ], [ undef, %b4 ]
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%v4 = tail call <32 x i32> @llvm.hexagon.V6.vmpyh(<16 x i32> undef, i32 undef)
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br label %b3
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b3: ; preds = %b3, %b2
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%v5 = phi <32 x i32> [ %v4, %b2 ], [ %v72, %b3 ]
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%v6 = phi <32 x i32> [ zeroinitializer, %b2 ], [ %v71, %b3 ]
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%v7 = phi i32 [ -4, %b2 ], [ %v73, %b3 ]
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%v8 = load <16 x i32>, <16 x i32>* undef, align 64
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%v9 = mul nsw i32 %v7, 9
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%v10 = tail call <16 x i32> @llvm.hexagon.V6.vlalignb(<16 x i32> %v8, <16 x i32> undef, i32 4)
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%v11 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> undef, <16 x i32> %v8, i32 4)
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%v12 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffub(<16 x i32> %v10, <16 x i32> undef)
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%v13 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffub(<16 x i32> %v11, <16 x i32> undef)
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%v14 = tail call <16 x i32> @llvm.hexagon.V6.vlutvvb(<16 x i32> %v12, <16 x i32> zeroinitializer, i32 0)
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%v15 = tail call <16 x i32> @llvm.hexagon.V6.vlutvvb.oracc(<16 x i32> %v14, <16 x i32> %v12, <16 x i32> zeroinitializer, i32 1)
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%v16 = tail call <16 x i32> @llvm.hexagon.V6.vlutvvb.oracc(<16 x i32> %v15, <16 x i32> %v12, <16 x i32> undef, i32 2)
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%v17 = tail call <16 x i32> @llvm.hexagon.V6.vlutvvb.oracc(<16 x i32> %v16, <16 x i32> %v12, <16 x i32> undef, i32 3)
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%v18 = tail call <16 x i32> @llvm.hexagon.V6.vlutvvb.oracc(<16 x i32> %v17, <16 x i32> %v12, <16 x i32> %v0, i32 4)
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%v19 = tail call <16 x i32> @llvm.hexagon.V6.vlutvvb.oracc(<16 x i32> %v18, <16 x i32> %v12, <16 x i32> %v0, i32 5)
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%v20 = tail call <16 x i32> @llvm.hexagon.V6.vlutvvb.oracc(<16 x i32> %v19, <16 x i32> %v12, <16 x i32> undef, i32 6)
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%v21 = tail call <16 x i32> @llvm.hexagon.V6.vlutvvb.oracc(<16 x i32> %v20, <16 x i32> %v12, <16 x i32> undef, i32 7)
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%v22 = tail call <16 x i32> @llvm.hexagon.V6.vlutvvb.oracc(<16 x i32> undef, <16 x i32> %v13, <16 x i32> %v0, i32 4)
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%v23 = tail call <16 x i32> @llvm.hexagon.V6.vlutvvb.oracc(<16 x i32> %v22, <16 x i32> %v13, <16 x i32> %v0, i32 5)
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%v24 = tail call <16 x i32> @llvm.hexagon.V6.vlutvvb.oracc(<16 x i32> %v23, <16 x i32> %v13, <16 x i32> undef, i32 6)
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%v25 = tail call <16 x i32> @llvm.hexagon.V6.vlutvvb.oracc(<16 x i32> %v24, <16 x i32> %v13, <16 x i32> undef, i32 7)
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%v26 = add nsw i32 %v9, 36
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%v27 = getelementptr inbounds i8, i8* %a3, i32 %v26
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%v28 = load i8, i8* %v27, align 1
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%v29 = zext i8 %v28 to i32
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%v30 = tail call i32 @llvm.hexagon.S2.vsplatrb(i32 %v29)
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%v31 = tail call <32 x i32> @llvm.hexagon.V6.vmpyub(<16 x i32> %v21, i32 %v30)
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%v32 = tail call <32 x i32> @llvm.hexagon.V6.vmpyub(<16 x i32> %v25, i32 %v30)
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%v33 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v31)
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%v34 = tail call <16 x i32> @llvm.hexagon.V6.vshuffob(<16 x i32> undef, <16 x i32> %v33)
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%v35 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v32)
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%v36 = tail call <16 x i32> @llvm.hexagon.V6.vshuffob(<16 x i32> %v35, <16 x i32> undef)
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%v37 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v36, <16 x i32> %v34)
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%v38 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32> %v6, <32 x i32> %v37, i32 16843009)
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%v39 = tail call <32 x i32> @llvm.hexagon.V6.vmpyubv(<16 x i32> %v10, <16 x i32> %v34)
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%v40 = tail call <32 x i32> @llvm.hexagon.V6.vmpyubv(<16 x i32> %v11, <16 x i32> %v36)
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%v41 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v39)
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%v42 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v40)
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%v43 = tail call <32 x i32> @llvm.hexagon.V6.vadduhw(<16 x i32> %v41, <16 x i32> %v42)
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%v44 = tail call <32 x i32> @llvm.hexagon.V6.vaddw.dv(<32 x i32> %v5, <32 x i32> %v43)
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%v45 = add nsw i32 %v9, 37
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%v46 = getelementptr inbounds i8, i8* %a3, i32 %v45
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%v47 = load i8, i8* %v46, align 1
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%v48 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32> %v38, <32 x i32> undef, i32 16843009)
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%v49 = tail call <32 x i32> @llvm.hexagon.V6.vaddw.dv(<32 x i32> %v44, <32 x i32> undef)
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%v50 = tail call <16 x i32> @llvm.hexagon.V6.vlalignb(<16 x i32> %v8, <16 x i32> undef, i32 2)
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%v51 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32> %v48, <32 x i32> undef, i32 16843009)
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%v52 = tail call <32 x i32> @llvm.hexagon.V6.vmpyubv(<16 x i32> %v50, <16 x i32> undef)
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%v53 = tail call <32 x i32> @llvm.hexagon.V6.vmpyubv(<16 x i32> undef, <16 x i32> zeroinitializer)
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%v54 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v52)
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%v55 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v53)
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%v56 = tail call <32 x i32> @llvm.hexagon.V6.vadduhw(<16 x i32> %v54, <16 x i32> %v55)
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%v57 = tail call <32 x i32> @llvm.hexagon.V6.vaddw.dv(<32 x i32> %v49, <32 x i32> %v56)
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%v58 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> undef, <16 x i32> %v8, i32 1)
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%v59 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffub(<16 x i32> %v58, <16 x i32> undef)
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%v60 = tail call <16 x i32> @llvm.hexagon.V6.vlutvvb.oracc(<16 x i32> undef, <16 x i32> %v59, <16 x i32> undef, i32 7)
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%v61 = load i8, i8* undef, align 1
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%v62 = zext i8 %v61 to i32
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%v63 = tail call i32 @llvm.hexagon.S2.vsplatrb(i32 %v62)
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%v64 = tail call <32 x i32> @llvm.hexagon.V6.vmpyub(<16 x i32> undef, i32 %v63)
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%v65 = tail call <32 x i32> @llvm.hexagon.V6.vmpyub(<16 x i32> %v60, i32 %v63)
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%v66 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v64)
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%v67 = tail call <16 x i32> @llvm.hexagon.V6.vshuffob(<16 x i32> undef, <16 x i32> %v66)
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%v68 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v65)
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%v69 = tail call <16 x i32> @llvm.hexagon.V6.vshuffob(<16 x i32> undef, <16 x i32> %v68)
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%v70 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v69, <16 x i32> %v67)
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%v71 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32> %v51, <32 x i32> %v70, i32 16843009)
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%v72 = tail call <32 x i32> @llvm.hexagon.V6.vaddw.dv(<32 x i32> %v57, <32 x i32> undef)
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%v73 = add nsw i32 %v7, 1
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%v74 = icmp eq i32 %v73, 5
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br i1 %v74, label %b4, label %b3
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b4: ; preds = %b3
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%v75 = phi <32 x i32> [ %v72, %b3 ]
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%v76 = phi <32 x i32> [ %v71, %b3 ]
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%v77 = load i8, i8* %v1, align 1
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%v78 = zext i8 %v77 to i32
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%v79 = tail call i32 @llvm.hexagon.S2.vsplatrb(i32 %v78)
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%v80 = tail call <32 x i32> @llvm.hexagon.V6.vmpyub(<16 x i32> undef, i32 %v79)
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%v81 = tail call <16 x i32> @llvm.hexagon.V6.vshuffob(<16 x i32> undef, <16 x i32> undef)
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%v82 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v80)
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%v83 = tail call <16 x i32> @llvm.hexagon.V6.vshuffob(<16 x i32> undef, <16 x i32> %v82)
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%v84 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v83, <16 x i32> %v81)
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%v85 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32> undef, <32 x i32> %v84, i32 16843009)
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%v86 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v85)
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%v87 = tail call <32 x i32> @llvm.hexagon.V6.vmpyh(<16 x i32> %v86, i32 8388736)
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%v88 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v87)
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%v89 = tail call <16 x i32> @llvm.hexagon.V6.vasrw(<16 x i32> %v88, i32 1)
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%v90 = tail call <16 x i32> @llvm.hexagon.V6.vasrw(<16 x i32> %v89, i32 1)
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%v91 = tail call <16 x i32> @llvm.hexagon.V6.vasrw(<16 x i32> %v90, i32 1)
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%v92 = tail call <16 x i32> @llvm.hexagon.V6.vasrw(<16 x i32> %v91, i32 1)
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%v93 = tail call <16 x i32> @llvm.hexagon.V6.vasrw(<16 x i32> %v92, i32 1)
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%v94 = tail call <16 x i32> @llvm.hexagon.V6.vsubwnq(<64 x i1> undef, <16 x i32> undef, <16 x i32> %v93)
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%v95 = tail call <16 x i32> @llvm.hexagon.V6.vsubwnq(<64 x i1> undef, <16 x i32> %v94, <16 x i32> undef)
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%v96 = tail call <16 x i32> @llvm.hexagon.V6.vasrw(<16 x i32> undef, i32 1)
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%v97 = tail call <64 x i1> @llvm.hexagon.V6.vgtw(<16 x i32> %v96, <16 x i32> %v95)
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%v98 = tail call <16 x i32> @llvm.hexagon.V6.vaddwnq(<64 x i1> %v97, <16 x i32> undef, <16 x i32> undef)
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%v99 = tail call <16 x i32> @llvm.hexagon.V6.vaddwnq(<64 x i1> undef, <16 x i32> undef, <16 x i32> undef)
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%v100 = tail call <16 x i32> @llvm.hexagon.V6.vshufeh(<16 x i32> %v99, <16 x i32> %v98)
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%v101 = tail call <16 x i32> @llvm.hexagon.V6.vshuffeb(<16 x i32> %v100, <16 x i32> undef)
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%v102 = getelementptr inbounds <16 x i32>, <16 x i32>* %v2, i32 1
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store <16 x i32> %v101, <16 x i32>* %v2, align 64
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%v103 = icmp sgt i32 %v3, 64
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br i1 %v103, label %b2, label %b5
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b5: ; preds = %b4, %b0
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ret void
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}
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vshuffb(<16 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <32 x i32> @llvm.hexagon.V6.vmpyh(<16 x i32>, i32) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32>, <16 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vlalignb(<16 x i32>, <16 x i32>, i32) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32>, <16 x i32>, i32) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vabsdiffub(<16 x i32>, <16 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vlutvvb(<16 x i32>, <16 x i32>, i32) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vlutvvb.oracc(<16 x i32>, <16 x i32>, <16 x i32>, i32) #1
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; Function Attrs: nounwind readnone
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declare i32 @llvm.hexagon.S2.vsplatrb(i32) #1
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; Function Attrs: nounwind readnone
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declare <32 x i32> @llvm.hexagon.V6.vmpyub(<16 x i32>, i32) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vshuffob(<16 x i32>, <16 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32>, <32 x i32>, i32) #1
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; Function Attrs: nounwind readnone
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declare <32 x i32> @llvm.hexagon.V6.vmpyubv(<16 x i32>, <16 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <32 x i32> @llvm.hexagon.V6.vaddw.dv(<32 x i32>, <32 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <32 x i32> @llvm.hexagon.V6.vadduhw(<16 x i32>, <16 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <64 x i1> @llvm.hexagon.V6.vgtw(<16 x i32>, <16 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vaddwnq(<64 x i1>, <16 x i32>, <16 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vsubwnq(<64 x i1>, <16 x i32>, <16 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vasrw(<16 x i32>, i32) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vshuffeb(<16 x i32>, <16 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vshufeh(<16 x i32>, <16 x i32>) #1
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attributes #0 = { nounwind "target-cpu"="hexagonv62" "target-features"="+hvxv62,+hvx-length64b" }
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attributes #1 = { nounwind readnone }
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