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62 lines
1.9 KiB
LLVM
62 lines
1.9 KiB
LLVM
; RUN: llc -march=hexagon --enable-pipeliner -hexagon-expand-condsets=0 < %s
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; REQUIRES: asserts
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; Disable expand-condsets because it will assert on undefined registers.
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define void @f0() #0 {
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b0:
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br i1 undef, label %b1, label %b2
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b1: ; preds = %b0
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unreachable
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b2: ; preds = %b0
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br i1 undef, label %b3, label %b4
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b3: ; preds = %b3, %b2
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br i1 undef, label %b4, label %b3
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b4: ; preds = %b3, %b2
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%v0 = ashr i32 undef, 25
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%v1 = mul nsw i32 %v0, 2
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%v2 = load i8, i8* undef, align 1
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br i1 undef, label %b5, label %b10
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b5: ; preds = %b4
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br i1 undef, label %b6, label %b9
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b6: ; preds = %b5
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br label %b7
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b7: ; preds = %b7, %b6
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br i1 undef, label %b7, label %b8
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b8: ; preds = %b7
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br i1 undef, label %b10, label %b9
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b9: ; preds = %b9, %b8, %b5
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%v3 = phi i8 [ %v7, %b9 ], [ undef, %b8 ], [ %v2, %b5 ]
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%v4 = phi i32 [ %v8, %b9 ], [ undef, %b8 ], [ 1, %b5 ]
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%v5 = add i32 %v4, undef
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%v6 = load i8, i8* undef, align 1
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%v7 = select i1 undef, i8 %v6, i8 %v3
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%v8 = add nsw i32 %v4, 1
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%v9 = icmp eq i32 %v8, %v1
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br i1 %v9, label %b10, label %b9
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b10: ; preds = %b9, %b8, %b4
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%v10 = phi i8 [ %v2, %b4 ], [ undef, %b8 ], [ %v7, %b9 ]
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br i1 false, label %b11, label %b12
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b11: ; preds = %b10
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unreachable
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b12: ; preds = %b10
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br label %b13
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b13: ; preds = %b13, %b12
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br label %b13
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv55" }
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