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6d4312d77f
This recommits 71ed4b6ce57d8843ef705af8f98305976a8f107a with the polarity of some of the pattern corrected. Original commit message: The custom expansion of select operations in the RISC-V backend interferes with the matching of cmov instructions. Legalizing select when the Zbt extension is available solves that problem. Reviewed By: luismarques, craig.topper Differential Revision: https://reviews.llvm.org/D93767
46 lines
1.3 KiB
LLVM
46 lines
1.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32I
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32IBT
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define i32 @bare_select(i1 %a, i32 %b, i32 %c) nounwind {
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; RV32I-LABEL: bare_select:
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; RV32I: # %bb.0:
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; RV32I-NEXT: andi a3, a0, 1
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; RV32I-NEXT: mv a0, a1
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; RV32I-NEXT: bnez a3, .LBB0_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: mv a0, a2
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; RV32I-NEXT: .LBB0_2:
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; RV32I-NEXT: ret
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;
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; RV32IBT-LABEL: bare_select:
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; RV32IBT: # %bb.0:
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; RV32IBT-NEXT: andi a0, a0, 1
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; RV32IBT-NEXT: cmov a0, a0, a1, a2
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; RV32IBT-NEXT: ret
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%1 = select i1 %a, i32 %b, i32 %c
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ret i32 %1
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}
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define float @bare_select_float(i1 %a, float %b, float %c) nounwind {
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; RV32I-LABEL: bare_select_float:
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; RV32I: # %bb.0:
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; RV32I-NEXT: andi a3, a0, 1
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; RV32I-NEXT: mv a0, a1
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; RV32I-NEXT: bnez a3, .LBB1_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: mv a0, a2
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; RV32I-NEXT: .LBB1_2:
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; RV32I-NEXT: ret
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;
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; RV32IBT-LABEL: bare_select_float:
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; RV32IBT: # %bb.0:
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; RV32IBT-NEXT: andi a0, a0, 1
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; RV32IBT-NEXT: cmov a0, a0, a1, a2
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; RV32IBT-NEXT: ret
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%1 = select i1 %a, float %b, float %c
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ret float %1
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}
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