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80d5f68422
Return is now considered a predicable instruction, and is converted to a newly-added CondReturn (which maps to BCR to %r14) instruction by the if conversion pass. Also, fused compare-and-branch transform knows about conditional returns, emitting the proper fused instructions for them. This transform triggers on a *lot* of tests, hence the huge diffstat. The changes are mostly jX to br %r14 -> bXr %r14. Author: koriakin Differential Revision: http://reviews.llvm.org/D17339 llvm-svn: 265689
353 lines
8.6 KiB
LLVM
353 lines
8.6 KiB
LLVM
; Test transactional-execution intrinsics.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 | FileCheck %s
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declare i32 @llvm.s390.tbegin(i8 *, i32)
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declare i32 @llvm.s390.tbegin.nofloat(i8 *, i32)
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declare void @llvm.s390.tbeginc(i8 *, i32)
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declare i32 @llvm.s390.tend()
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declare void @llvm.s390.tabort(i64)
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declare void @llvm.s390.ntstg(i64, i64 *)
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declare i32 @llvm.s390.etnd()
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declare void @llvm.s390.ppa.txassist(i32)
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; TBEGIN.
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define void @test_tbegin() {
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; CHECK-LABEL: test_tbegin:
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; CHECK-NOT: stmg
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; CHECK: std %f8,
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; CHECK: std %f9,
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; CHECK: std %f10,
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; CHECK: std %f11,
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; CHECK: std %f12,
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; CHECK: std %f13,
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; CHECK: std %f14,
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; CHECK: std %f15,
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; CHECK: tbegin 0, 65292
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; CHECK: ld %f8,
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; CHECK: ld %f9,
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; CHECK: ld %f10,
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; CHECK: ld %f11,
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; CHECK: ld %f12,
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; CHECK: ld %f13,
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; CHECK: ld %f14,
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; CHECK: ld %f15,
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; CHECK: br %r14
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call i32 @llvm.s390.tbegin(i8 *null, i32 65292)
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ret void
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}
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; TBEGIN (nofloat).
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define void @test_tbegin_nofloat1() {
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; CHECK-LABEL: test_tbegin_nofloat1:
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; CHECK-NOT: stmg
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; CHECK-NOT: std
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; CHECK: tbegin 0, 65292
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; CHECK: br %r14
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call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292)
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ret void
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}
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; TBEGIN (nofloat) with integer CC return value.
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define i32 @test_tbegin_nofloat2() {
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; CHECK-LABEL: test_tbegin_nofloat2:
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; CHECK-NOT: stmg
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; CHECK-NOT: std
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; CHECK: tbegin 0, 65292
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; CHECK: ipm %r2
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; CHECK: srl %r2, 28
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; CHECK: br %r14
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%res = call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292)
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ret i32 %res
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}
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; TBEGIN (nofloat) with implicit CC check.
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define void @test_tbegin_nofloat3(i32 *%ptr) {
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; CHECK-LABEL: test_tbegin_nofloat3:
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; CHECK-NOT: stmg
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; CHECK-NOT: std
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; CHECK: tbegin 0, 65292
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; CHECK: bnhr %r14
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; CHECK: mvhi 0(%r2), 0
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; CHECK: br %r14
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%res = call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292)
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%cmp = icmp eq i32 %res, 2
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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store i32 0, i32* %ptr, align 4
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br label %if.end
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if.end: ; preds = %if.then, %entry
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ret void
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}
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; TBEGIN (nofloat) with dual CC use.
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define i32 @test_tbegin_nofloat4(i32 %pad, i32 *%ptr) {
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; CHECK-LABEL: test_tbegin_nofloat4:
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; CHECK-NOT: stmg
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; CHECK-NOT: std
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; CHECK: tbegin 0, 65292
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; CHECK: ipm %r2
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; CHECK: srl %r2, 28
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; CHECK: ciblh %r2, 2, 0(%r14)
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; CHECK: mvhi 0(%r3), 0
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; CHECK: br %r14
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%res = call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292)
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%cmp = icmp eq i32 %res, 2
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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store i32 0, i32* %ptr, align 4
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br label %if.end
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if.end: ; preds = %if.then, %entry
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ret i32 %res
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}
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; TBEGIN (nofloat) with register.
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define void @test_tbegin_nofloat5(i8 *%ptr) {
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; CHECK-LABEL: test_tbegin_nofloat5:
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; CHECK-NOT: stmg
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; CHECK-NOT: std
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; CHECK: tbegin 0(%r2), 65292
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; CHECK: br %r14
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call i32 @llvm.s390.tbegin.nofloat(i8 *%ptr, i32 65292)
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ret void
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}
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; TBEGIN (nofloat) with GRSM 0x0f00.
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define void @test_tbegin_nofloat6() {
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; CHECK-LABEL: test_tbegin_nofloat6:
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; CHECK: stmg %r6, %r15,
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; CHECK-NOT: std
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; CHECK: tbegin 0, 3840
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; CHECK: br %r14
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call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 3840)
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ret void
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}
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; TBEGIN (nofloat) with GRSM 0xf100.
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define void @test_tbegin_nofloat7() {
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; CHECK-LABEL: test_tbegin_nofloat7:
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; CHECK: stmg %r8, %r15,
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; CHECK-NOT: std
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; CHECK: tbegin 0, 61696
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; CHECK: br %r14
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call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 61696)
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ret void
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}
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; TBEGIN (nofloat) with GRSM 0xfe00 -- stack pointer added automatically.
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define void @test_tbegin_nofloat8() {
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; CHECK-LABEL: test_tbegin_nofloat8:
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; CHECK-NOT: stmg
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; CHECK-NOT: std
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; CHECK: tbegin 0, 65280
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; CHECK: br %r14
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call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65024)
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ret void
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}
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; TBEGIN (nofloat) with GRSM 0xfb00 -- no frame pointer needed.
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define void @test_tbegin_nofloat9() {
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; CHECK-LABEL: test_tbegin_nofloat9:
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; CHECK: stmg %r10, %r15,
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; CHECK-NOT: std
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; CHECK: tbegin 0, 64256
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; CHECK: br %r14
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call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 64256)
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ret void
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}
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; TBEGIN (nofloat) with GRSM 0xfb00 -- frame pointer added automatically.
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define void @test_tbegin_nofloat10(i64 %n) {
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; CHECK-LABEL: test_tbegin_nofloat10:
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; CHECK: stmg %r11, %r15,
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; CHECK-NOT: std
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; CHECK: tbegin 0, 65280
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; CHECK: br %r14
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%buf = alloca i8, i64 %n
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call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 64256)
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ret void
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}
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; TBEGINC.
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define void @test_tbeginc() {
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; CHECK-LABEL: test_tbeginc:
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; CHECK-NOT: stmg
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; CHECK-NOT: std
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; CHECK: tbeginc 0, 65288
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; CHECK: br %r14
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call void @llvm.s390.tbeginc(i8 *null, i32 65288)
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ret void
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}
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; TEND with integer CC return value.
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define i32 @test_tend1() {
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; CHECK-LABEL: test_tend1:
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; CHECK: tend
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; CHECK: ipm %r2
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; CHECK: srl %r2, 28
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; CHECK: br %r14
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%res = call i32 @llvm.s390.tend()
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ret i32 %res
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}
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; TEND with implicit CC check.
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define void @test_tend3(i32 *%ptr) {
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; CHECK-LABEL: test_tend3:
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; CHECK: tend
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; CHECK: ber %r14
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; CHECK: mvhi 0(%r2), 0
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; CHECK: br %r14
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%res = call i32 @llvm.s390.tend()
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%cmp = icmp eq i32 %res, 2
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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store i32 0, i32* %ptr, align 4
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br label %if.end
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if.end: ; preds = %if.then, %entry
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ret void
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}
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; TEND with dual CC use.
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define i32 @test_tend2(i32 %pad, i32 *%ptr) {
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; CHECK-LABEL: test_tend2:
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; CHECK: tend
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; CHECK: ipm %r2
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; CHECK: srl %r2, 28
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; CHECK: ciblh %r2, 2, 0(%r14)
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; CHECK: mvhi 0(%r3), 0
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; CHECK: br %r14
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%res = call i32 @llvm.s390.tend()
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%cmp = icmp eq i32 %res, 2
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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store i32 0, i32* %ptr, align 4
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br label %if.end
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if.end: ; preds = %if.then, %entry
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ret i32 %res
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}
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; TABORT with register only.
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define void @test_tabort1(i64 %val) {
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; CHECK-LABEL: test_tabort1:
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; CHECK: tabort 0(%r2)
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; CHECK: br %r14
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call void @llvm.s390.tabort(i64 %val)
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ret void
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}
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; TABORT with immediate only.
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define void @test_tabort2(i64 %val) {
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; CHECK-LABEL: test_tabort2:
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; CHECK: tabort 1234
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; CHECK: br %r14
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call void @llvm.s390.tabort(i64 1234)
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ret void
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}
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; TABORT with register + immediate.
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define void @test_tabort3(i64 %val) {
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; CHECK-LABEL: test_tabort3:
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; CHECK: tabort 1234(%r2)
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; CHECK: br %r14
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%sum = add i64 %val, 1234
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call void @llvm.s390.tabort(i64 %sum)
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ret void
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}
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; TABORT with out-of-range immediate.
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define void @test_tabort4(i64 %val) {
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; CHECK-LABEL: test_tabort4:
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; CHECK: tabort 0({{%r[1-5]}})
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; CHECK: br %r14
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call void @llvm.s390.tabort(i64 4096)
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ret void
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}
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; NTSTG with base pointer only.
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define void @test_ntstg1(i64 *%ptr, i64 %val) {
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; CHECK-LABEL: test_ntstg1:
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; CHECK: ntstg %r3, 0(%r2)
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; CHECK: br %r14
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call void @llvm.s390.ntstg(i64 %val, i64 *%ptr)
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ret void
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}
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; NTSTG with base and index.
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; Check that VSTL doesn't allow an index.
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define void @test_ntstg2(i64 *%base, i64 %index, i64 %val) {
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; CHECK-LABEL: test_ntstg2:
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; CHECK: sllg [[REG:%r[1-5]]], %r3, 3
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; CHECK: ntstg %r4, 0([[REG]],%r2)
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; CHECK: br %r14
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%ptr = getelementptr i64, i64 *%base, i64 %index
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call void @llvm.s390.ntstg(i64 %val, i64 *%ptr)
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ret void
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}
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; NTSTG with the highest in-range displacement.
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define void @test_ntstg3(i64 *%base, i64 %val) {
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; CHECK-LABEL: test_ntstg3:
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; CHECK: ntstg %r3, 524280(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i64, i64 *%base, i64 65535
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call void @llvm.s390.ntstg(i64 %val, i64 *%ptr)
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ret void
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}
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; NTSTG with an out-of-range positive displacement.
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define void @test_ntstg4(i64 *%base, i64 %val) {
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; CHECK-LABEL: test_ntstg4:
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; CHECK: ntstg %r3, 0({{%r[1-5]}})
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; CHECK: br %r14
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%ptr = getelementptr i64, i64 *%base, i64 65536
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call void @llvm.s390.ntstg(i64 %val, i64 *%ptr)
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ret void
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}
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; NTSTG with the lowest in-range displacement.
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define void @test_ntstg5(i64 *%base, i64 %val) {
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; CHECK-LABEL: test_ntstg5:
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; CHECK: ntstg %r3, -524288(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i64, i64 *%base, i64 -65536
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call void @llvm.s390.ntstg(i64 %val, i64 *%ptr)
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ret void
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}
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; NTSTG with an out-of-range negative displacement.
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define void @test_ntstg6(i64 *%base, i64 %val) {
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; CHECK-LABEL: test_ntstg6:
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; CHECK: ntstg %r3, 0({{%r[1-5]}})
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; CHECK: br %r14
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%ptr = getelementptr i64, i64 *%base, i64 -65537
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call void @llvm.s390.ntstg(i64 %val, i64 *%ptr)
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ret void
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}
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; ETND.
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define i32 @test_etnd() {
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; CHECK-LABEL: test_etnd:
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; CHECK: etnd %r2
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; CHECK: br %r14
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%res = call i32 @llvm.s390.etnd()
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ret i32 %res
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}
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; PPA (Transaction-Abort Assist)
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define void @test_ppa_txassist(i32 %val) {
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; CHECK-LABEL: test_ppa_txassist:
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; CHECK: ppa %r2, 0, 1
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; CHECK: br %r14
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call void @llvm.s390.ppa.txassist(i32 %val)
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ret void
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}
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