Petar Jovanovic 53474bdb0f [mips] Add madd4 subtarget feature ... Addition of a feature and a predicate used to control generation of madd.fmt and similar instructions. Patch by Stefan Maksimovic. Differential Revision: https://reviews.llvm.org/D33400 llvm-svn: 304801		2017-06-06 15:33:01 +00:00
..
AArch64	[Improve CodeGen Testing] This patch renables MIRPrinter print fields which have value equal to its default.	2017-06-06 08:16:19 +00:00
AMDGPU	AMDGPU/GlobalISel: Mark 32-bit G_ICMP as legal	2017-06-06 14:16:50 +00:00
ARM	[Improve CodeGen Testing] This patch renables MIRPrinter print fields which have value equal to its default.	2017-06-06 08:16:19 +00:00
AVR	[AVR] Fix a big in shift operator lowering; Authored by Dr. Gergo Erdi	2017-05-31 06:27:46 +00:00
BPF
Generic	CodeGen/LLVMTargetMachine: Refactor ISel pass construction; NFCI	2017-06-06 00:26:13 +00:00
Hexagon	[Hexagon] Return 0 from getDotNewPredOp when .new opcode does not exist	2017-06-02 14:07:06 +00:00
Inputs
Lanai
Mips	[mips] Add madd4 subtarget feature	2017-06-06 15:33:01 +00:00
MIR	[Improve CodeGen Testing] This patch renables MIRPrinter print fields which have value equal to its default.	2017-06-06 08:16:19 +00:00
MSP430
Nios2
NVPTX
PowerPC	RegisterScavenging: Add ScavengerTest pass	2017-06-02 23:01:42 +00:00
SPARC
SystemZ	[SystemZ] Simplify test case. NFC	2017-06-02 23:40:58 +00:00
Thumb
Thumb2	MIR: remove explicit "noVRegs" property.	2017-05-30 21:28:57 +00:00
WebAssembly
WinEH
X86	[X86][AVX1] Split 256-bit vector non-temporal FastISel loads to keep it non-temporal (PR32744)	2017-06-06 14:18:39 +00:00
XCore