llvm-mirror

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History

Craig Topper 38e5713f51 [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.

Summary:
This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between Jcc instructions and condition codes.

Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser.

Reviewers: spatel, lebedev.ri, courbet, gchatelet, RKSimon

Reviewed By: RKSimon

Subscribers: MatzeB, qcolombet, eraman, hiraditya, arphaman, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60228

llvm-svn: 357802

2019-04-05 19:28:09 +00:00

AArch64

MIR: Validate LLT types when parsing

2019-02-04 22:59:56 +00:00

AMDGPU

AMDGPU: Don't use the default cpu in a few tests

2019-04-03 00:00:58 +00:00

ARM

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

Generic

[codeview] Emit S_FRAMEPROC and use S_DEFRANGE_FRAMEPOINTER_REL

2018-10-01 21:59:45 +00:00

Hexagon

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

Mips

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

NVPTX

[MIR] Repurposing '$' sigil used by external symbols. Replacing with '&'.

2018-01-10 00:56:48 +00:00

PowerPC

[Power9] Allow gpr callee saved spills in prologue to vectors registers

2018-11-09 16:36:24 +00:00

WebAssembly

[MIRParser][GlobalISel] Parsing vector pointer types (<M x pA>)

2018-05-08 02:02:50 +00:00

X86

[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.

2019-04-05 19:28:09 +00:00

README

Add README describing the intention of test/CodeGen/MIR

2016-12-09 20:16:12 +00:00

README

This directory contains tests for the MIR file format parser and printer. It
was necessary to split the tests across different targets as no single target
covers all features available in machine IR.

Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As
a rule of thumb this directory should only contain tests using
'llc -run-pass none'.