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llvm-mirror/test/CodeGen
Bjorn Pettersson 6d1749e6c0 [SelectionDAG] Fix miscompile bugs related to smul.fix.sat with scale zero
When expanding a SMULFIXSAT ISD node (usually originating from
a smul.fix.sat intrinsic) we've applied some optimizations for
the special case when the scale is zero. The idea has been that
it would be cheaper to use an SMULO instruction (if legal) to
perform the multiplication and at the same time detect any overflow.
And in case of overflow we could use some SELECT:s to replace the
result with the saturated min/max value. The only tricky part
is to know if we overflowed on the min or max value, i.e. if the
product is positive or negative. Unfortunately the implementation
has been incorrect as it has looked at the product returned by the
SMULO to determine the sign of the product. In case of overflow that
product is truncated and won't give us the correct sign bit.

This patch is adding an extra XOR of the multiplication operands,
which is used to determine the sign of the non truncated product.

This patch fixes PR51677.

Reviewed By: lebedev.ri

Differential Revision: https://reviews.llvm.org/D108938

(cherry picked from commit 789f01283d52065b10049b58a3288c4abd1ef351)
2021-08-31 20:59:28 -07:00
..
AArch64 [AArch64] Fix comparison peephole opt with non-0/1 immediate (PR51476) 2021-08-18 20:07:23 -07:00
AMDGPU AMDGPU/GlobalISel: Fix selecting G_SEXTLOAD/G_ZEXTLOAD pre-gfx9 2021-07-27 15:56:42 -04:00
ARC
ARM [ARM][atomicrmw] Fix CMP_SWAP_32 expand assert 2021-08-18 12:14:24 -07:00
AVR
BPF BPF: avoid NE/EQ loop exit condition 2021-08-06 12:45:53 -07:00
Generic [PowerPC] Add pwr7 and pwr10 support to IBM MASSV pass on AIX 2021-07-26 23:21:38 +00:00
Hexagon [Hexagon] Fix resetting dead registers in DBG_VALUE_LISTs 2021-07-27 18:36:28 -05:00
Inputs
Lanai
M68k
Mips
MIR
MSP430
NVPTX
PowerPC [PowerPC] Disable CTR Loop generate for fma with the PPC double double type. 2021-08-17 20:22:13 -07:00
RISCV Revert "[RISCV] Fix reporting of incorrect commutable operand indices" 2021-08-24 21:59:54 -07:00
SPARC
SystemZ [SystemZ][z/OS] Initial code to generate assembly files on z/OS 2021-07-27 11:29:15 -04:00
Thumb
Thumb2 [ARM] Implement isLoad/StoreFromStackSlot for MVE stack stores accesses 2021-07-27 09:11:58 +01:00
VE
WebAssembly [WebAssembly] Fix FastISel of condition in different block (PR51651) 2021-08-31 20:58:25 -07:00
WinCFGuard
WinEH
X86 [SelectionDAG] Fix miscompile bugs related to smul.fix.sat with scale zero 2021-08-31 20:59:28 -07:00
XCore