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https://github.com/RPCS3/llvm-mirror.git
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3f31269929
This patch adds support for following contiguous load and store instructions: * LD1B, LD1H, LD1W, LD1D, LD1Q * ST1B, ST1H, ST1W, ST1D, ST1Q A new register class and operand is added for the 32-bit vector select register W12-W15. The differences in the following tests which have been re-generated are caused by the introduction of this register class: * llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll * llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir * llvm/test/CodeGen/AArch64/stp-opt-with-renaming-reserved-regs.mir * llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir D88663 attempts to resolve the issue with the store pair test differences in the AArch64 load/store optimizer. The GlobalISel differences are caused by changes in the enum values of register classes, tests have been updated with the new values. The reference can be found here: https://developer.arm.com/documentation/ddi0602/2021-06 Reviewed By: CarolineConcatto Differential Revision: https://reviews.llvm.org/D105572
53 lines
2.1 KiB
ArmAsm
53 lines
2.1 KiB
ArmAsm
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme,+sme-i64 2>&1 < %s| FileCheck %s
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// ------------------------------------------------------------------------- //
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// Invalid tile
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addha za4.s, p0/m, p0/m, z0.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: addha za4.s, p0/m, p0/m, z0.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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addha za8.d, p0/m, p0/m, z0.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: addha za8.d, p0/m, p0/m, z0.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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addha za0p.s, p0/m, p0/m, z0.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: addha za0p.s, p0/m, p0/m, z0.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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addha za0h.s, p0/m, p0/m, z0.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-7].d
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// CHECK-NEXT: addha za0h.s, p0/m, p0/m, z0.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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addha za0v.s, p0/m, p0/m, z0.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-7].d
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// CHECK-NEXT: addha za0v.s, p0/m, p0/m, z0.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// Invalid predicate
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addha za0.s, p8/m, p0/m, z0.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: addha za0.s, p8/m, p0/m, z0.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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addha za0.s, p0/m, p8/m, z0.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: addha za0.s, p0/m, p8/m, z0.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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addha za0.d, p8/m, p0/m, z0.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: addha za0.d, p8/m, p0/m, z0.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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addha za0.d, p0/m, p8/m, z0.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: addha za0.d, p0/m, p8/m, z0.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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