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c55c74c634
This patch adds support for the following outer product instructions:
* BFMOPA, BFMOPS, FMOPA, FMOPS, SMOPA, SMOPS, SUMOPA, SUMOPS, UMOPA,
UMOPS, USMOPA, USMOPS.
Depends on D105570.
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2021-06
Reviewed By: david-arm
Differential Revision: https://reviews.llvm.org/D105571
88 lines
3.5 KiB
ArmAsm
88 lines
3.5 KiB
ArmAsm
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme,+sme-i64 2>&1 < %s| FileCheck %s
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// ------------------------------------------------------------------------- //
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// Invalid tile
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//
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// expected: .s => za0-za3, .d => za0-za7
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usmops za4.s, p0/m, p0/m, z0.b, z0.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: usmops za4.s, p0/m, p0/m, z0.b, z0.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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usmops za8.d, p0/m, p0/m, z0.h, z0.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: usmops za8.d, p0/m, p0/m, z0.h, z0.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// Invalid predicate (expected: p0-p7)
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usmops za0.s, p8/m, p0/m, z0.b, z0.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: usmops za0.s, p8/m, p0/m, z0.b, z0.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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usmops za0.s, p0/m, p8/m, z0.b, z0.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: usmops za0.s, p0/m, p8/m, z0.b, z0.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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usmops za0.d, p8/m, p0/m, z0.h, z0.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: usmops za0.d, p8/m, p0/m, z0.h, z0.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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usmops za0.d, p0/m, p8/m, z0.h, z0.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: usmops za0.d, p0/m, p8/m, z0.h, z0.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// Invalid predicate qualifier (expected: /m)
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usmops za0.s, p0/z, p0/m, z0.b, z0.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: usmops za0.s, p0/z, p0/m, z0.b, z0.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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usmops za0.s, p0/m, p0/z, z0.b, z0.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: usmops za0.s, p0/m, p0/z, z0.b, z0.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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usmops za0.d, p0/z, p0/m, z0.h, z0.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: usmops za0.d, p0/z, p0/m, z0.h, z0.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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usmops za0.d, p0/m, p0/z, z0.h, z0.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: usmops za0.d, p0/m, p0/z, z0.h, z0.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// Invalid ZPR type suffix
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//
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// expected: .s => .b, .d => .h
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usmops za0.s, p0/m, p0/m, z0.h, z0.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: usmops za0.s, p0/m, p0/m, z0.h, z0.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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usmops za0.s, p0/m, p0/m, z0.b, z0.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: usmops za0.s, p0/m, p0/m, z0.b, z0.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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usmops za0.d, p0/m, p0/m, z0.b, z0.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: usmops za0.d, p0/m, p0/m, z0.b, z0.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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usmops za0.d, p0/m, p0/m, z0.h, z0.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: usmops za0.d, p0/m, p0/m, z0.h, z0.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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