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6fb2b88ccc
This patch fixes an assembler bug that allowed SVE vector registers to contain a
type suffix when not expected. The SVE unpredicated movprfx instruction is the
only instruction affected.
The following are examples of what was previously valid:
movprfx z0.b, z0.b
movprfx z0.b, z0.s
movprfx z0, z0.s
These instructions are now erroneous.
Patch by Cullen Rhodes (c-rhodes)
Reviewed By: sdesmalen
Differential Revision: https://reviews.llvm.org/D59636
llvm-svn: 357094
33 lines
1.3 KiB
ArmAsm
33 lines
1.3 KiB
ArmAsm
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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// --------------------------------------------------------------------------//
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// Immediate out of upper bound [-256, 255].
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ldr p0, [x0, #-257, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-256, 255].
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// CHECK-NEXT: ldr p0, [x0, #-257, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ldr p0, [x0, #256, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-256, 255].
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// CHECK-NEXT: ldr p0, [x0, #256, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ldr z0, [x0, #-257, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-256, 255].
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// CHECK-NEXT: ldr z0, [x0, #-257, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ldr z0, [x0, #256, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-256, 255].
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// CHECK-NEXT: ldr z0, [x0, #256, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Unexpected element width suffix
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ldr z0.b, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected register without element width suffix
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// CHECK-NEXT: ldr z0.b, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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