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llvm-mirror/test/MC/AArch64/SVE/sel-diagnostics.s
Cullen Rhodes 899b2f53e8 [AArch64][AsmParser] error on unexpected SVE predicate type suffix
Summary:
This patch fixes a bug in the assembler that permitted a type suffix on
predicate registers when not expected. For instance, the following was
previously valid:

    faddv h0, p0.q, z1.h

This bug was present in all SVE instructions containing predicates with
no type suffix and no predication form qualifier, i.e. /z or /m. The
latter instructions are already caught with an appropiate error message
by the assembler, e.g.:

            .text
    <stdin>:1:13: error: not expecting size suffix
    cmpne p1.s, p0.b/z, z2.s, 0
                ^

A similar issue for SVE vector registers was fixed in:

  https://reviews.llvm.org/D59636

Reviewed By: SjoerdMeijer

Differential Revision: https://reviews.llvm.org/D62942

llvm-svn: 362780
2019-06-07 08:46:56 +00:00

41 lines
1.6 KiB
ArmAsm

// RUN: not llvm-mc -triple=aarch64-none-linux-gnu -show-encoding -mattr=+sve 2>&1 < %s | FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid predicate operand
sel z0.b, p0.b, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
// CHECK-NEXT: sel z0.b, p0.b, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sel z0.b, p0.q, z0.b, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
// CHECK-NEXT: sel z0.b, p0.q, z0.b, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sel p0.b, p0.b, p0.b, p0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
// CHECK-NEXT: sel p0.b, p0.b, p0.b, p0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sel p0.b, p0.q, p0.b, p0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
// CHECK-NEXT: sel p0.b, p0.q, p0.b, p0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z28.b, p7/z, z30.b
sel z28.b, p7, z13.b, z8.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sel z28.b, p7, z13.b, z8.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z23, z30
sel z23.b, p11, z13.b, z8.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: sel z23.b, p11, z13.b, z8.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: