Matt Arsenault fdc405fac4 AMDGPU/GlobalISel: Use less artifical example to avoid abort=0 ...

These were failing due to an unlegalizable G_CONCAT_VECTORS due to
registers with types that are naturally illegal.

2020-06-15 07:37:15 -04:00

..

AArch64

[MachineVerifier][GlobalISel] Check that branches have a MBB operand or are declared indirect. Add missing properties to G_BRJT, G_BRINDIRECT

2020-06-15 11:17:09 +02:00

AMDGPU

AMDGPU/GlobalISel: Use less artifical example to avoid abort=0

2020-06-15 07:37:15 -04:00

ARC

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ARM

[DAGCombine] Generalize the case (add (or x, c1), c2) -> (add x, (c1 + c2))

2020-06-12 13:53:08 -04:00

AVR

[AVR][test] Remove test for naked function containing a return.

2020-06-09 09:06:47 +01:00

BPF

[BPF] fix incorrect type in BPFISelDAGToDAG readonly load optimization

2020-06-11 19:31:06 -07:00

Generic

[Tests] Migrate a number of tests to gc-live bundle representation

2020-06-05 16:44:04 -07:00

Hexagon

Simplify MachineVerifier's block-successor verification.

2020-06-06 22:30:51 -04:00

Inputs

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Lanai

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Mips

[DAGCombine] Generalize the case (add (or x, c1), c2) -> (add x, (c1 + c2))

2020-06-12 13:53:08 -04:00

MIR

[MachineVerifier] Verify that a DBG_VALUE has a debug location

2020-05-28 13:53:40 -07:00

MSP430

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NVPTX

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PowerPC

[PowerPC] fma chain break to expose more ILP

2020-06-15 00:00:04 -04:00

RISCV

[DAGCombine] Generalize the case (add (or x, c1), c2) -> (add x, (c1 + c2))

2020-06-12 13:53:08 -04:00

SPARC

[SPARC] Lower fp16 ops to libcalls

2020-06-10 19:15:26 -07:00

SystemZ

[CostModel] Unify Shuffle and InsertElement Costs

2020-06-10 09:13:34 +01:00

Thumb

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Thumb2

[ARM] Add some MVE vecreduce tests. NFC

2020-06-09 12:07:19 +01:00

VE

[VE] Support relocation information in MC layer

2020-06-15 11:24:53 +02:00

WebAssembly

[WebAssembly] Make BR_TABLE non-duplicable

2020-06-11 15:11:45 -07:00

WinCFGuard

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WinEH

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X86

[X86][SSE] Add tests for and/or reduction results compared to zero

2020-06-15 10:40:45 +01:00

XCore

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