Jun Bum Lim 3cdf780204 [AArch64] Promote loads from stored ... This is a recommit of r256004 which was reverted in r256160. The issue was the incorrect promotion for half and byte loads transformed into mov instructions. This fix will replace half and byte type loads only with bit field extracts. Original commit message: This change promotes load instructions which directly read from stored by replacing them with mov instructions. If the store is wider than the load, the load will be replaced with a bitfield extract. For example : STRWui %W1, %X0, 1 %W0 = LDRHHui %X0, 3 becomes STRWui %W1, %X0, 1 %W0 = UBFMWri %W1, 16, 31 llvm-svn: 256249		2015-12-22 16:36:16 +00:00
..
AsmParser	[AArch64] Add ARMv8.2-A FP16 vector instructions	2015-12-08 12:16:10 +00:00
Disassembler	[AArch64] Add ARMv8.2-A UAO PSTATE bit	2015-11-26 15:32:30 +00:00
InstPrinter	[AArch64] Add ARMv8.2-A Statistical Profiling Extension	2015-12-01 10:48:51 +00:00
MCTargetDesc	[AArch64] Add ARMv8.2-A FP16 scalar instructions	2015-11-27 13:04:48 +00:00
TargetInfo
Utils	[AArch64] Add ARMv8.2-A Statistical Profiling Extension	2015-12-01 10:48:51 +00:00
AArch64.h
AArch64.td	[AArch64]: Add support for Cortex-A35	2015-12-02 11:53:44 +00:00
AArch64A53Fix835769.cpp
AArch64A57FPLoadBalancing.cpp
AArch64AddressTypePromotion.cpp
AArch64AdvSIMDScalarPass.cpp
AArch64AsmPrinter.cpp
AArch64BranchRelaxation.cpp
AArch64CallingConvention.h	Replace uint16_t with the MCPhysReg typedef in many places. A lot of physical register arrays already use this typedef.	2015-12-05 07:13:35 +00:00
AArch64CallingConvention.td	CXX_FAST_TLS calling convention: performance improvement for AArch64.	2015-12-16 21:04:19 +00:00
AArch64CleanupLocalDynamicTLSPass.cpp
AArch64CollectLOH.cpp
AArch64ConditionalCompares.cpp	Normalize MBB's successors' probabilities in several locations.	2015-12-13 09:26:17 +00:00
AArch64ConditionOptimizer.cpp
AArch64DeadRegisterDefinitionsPass.cpp
AArch64ExpandPseudoInsts.cpp
AArch64FastISel.cpp	CXX_FAST_TLS calling convention: performance improvement for AArch64.	2015-12-16 21:04:19 +00:00
AArch64FrameLowering.cpp	AArch64: Simplify emitEpilogue() and related code; NFC	2015-12-17 03:18:47 +00:00
AArch64FrameLowering.h	[AArch64] Enable shrink-wrapping by default.	2015-11-18 23:12:20 +00:00
AArch64InstrAtomics.td
AArch64InstrFormats.td	[AArch64] Fix FP16 vector instructions that should only accept low registers	2015-12-09 14:32:11 +00:00
AArch64InstrInfo.cpp
AArch64InstrInfo.h
AArch64InstrInfo.td	[AArch64] Add additional extract-extend patterns for smov	2015-12-21 18:31:25 +00:00
AArch64ISelDAGToDAG.cpp	[AArch64] Fix a corner case in BitFeild select	2015-12-01 19:17:49 +00:00
AArch64ISelLowering.cpp	Revert "[AArch64] Add DAG combine for extract extend pattern"	2015-12-17 21:29:47 +00:00
AArch64ISelLowering.h	CXX_FAST_TLS calling convention: performance improvement for AArch64.	2015-12-16 21:04:19 +00:00
AArch64LoadStoreOptimizer.cpp	[AArch64] Promote loads from stored	2015-12-22 16:36:16 +00:00
AArch64MachineFunctionInfo.h	CXX_FAST_TLS calling convention: performance improvement for AArch64.	2015-12-16 21:04:19 +00:00
AArch64MCInstLower.cpp
AArch64MCInstLower.h
AArch64PBQPRegAlloc.cpp
AArch64PBQPRegAlloc.h
AArch64PerfectShuffle.h
AArch64PromoteConstant.cpp
AArch64RegisterInfo.cpp	CXX_FAST_TLS calling convention: performance improvement for AArch64.	2015-12-16 21:04:19 +00:00
AArch64RegisterInfo.h	CXX_FAST_TLS calling convention: performance improvement for AArch64.	2015-12-16 21:04:19 +00:00
AArch64RegisterInfo.td	[AArch64] Add ARMv8.2-A FP16 vector instructions	2015-12-08 12:16:10 +00:00
AArch64SchedA53.td
AArch64SchedA57.td
AArch64SchedA57WriteRes.td
AArch64SchedCyclone.td
AArch64Schedule.td
AArch64SelectionDAGInfo.cpp
AArch64SelectionDAGInfo.h
AArch64StorePairSuppress.cpp
AArch64Subtarget.cpp	[AArch64] Add subtarget features for ARMv8.2-A	2015-11-26 15:23:32 +00:00
AArch64Subtarget.h	[AArch64] Enable PostRAScheduler for AArch64 generic build.	2015-12-21 14:43:45 +00:00
AArch64TargetMachine.cpp
AArch64TargetMachine.h
AArch64TargetObjectFile.cpp
AArch64TargetObjectFile.h
AArch64TargetTransformInfo.cpp	[AArch64][ARM] Don't base interleaved op legality on type alloc size.	2015-12-09 01:19:50 +00:00
AArch64TargetTransformInfo.h
CMakeLists.txt
LLVMBuild.txt
Makefile