Daniel Sanders fe8b495815 [mips] Add cache and pref instructions ...

Summary:
cache and pref were added in MIPS-III, and MIPS32 but were re-encoded in
MIPS32r6/MIPS64r6 to use a 9-bit offset rather than the 16-bit offset
available to earlier cores.

Resolved the decoding conflict between pref and lwc3.

Depends on D4115

Reviewers: zoran.jovanovic, jkolek, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D4116

llvm-svn: 210900

2014-06-13 13:15:59 +00:00

..

invalid-mips4.s

[mips][mips64r6] bc1[tf] are not available on MIPS32r6/MIPS64r6

2014-06-12 15:00:17 +00:00

invalid-mips5-wrong-error.s

[mips] Marked up instructions added in MIPS-V and tested that IAS for -mcpu=mips[1234] does not accept them

2014-05-12 12:52:44 +00:00

invalid-mips5.s

[mips][mips64r6] bc1[tf] are not available on MIPS32r6/MIPS64r6

2014-06-12 15:00:17 +00:00

valid.s

[mips] Add cache and pref instructions

2014-06-13 13:15:59 +00:00