Daniel Sanders fe8b495815 [mips] Add cache and pref instructions ...

Summary:
cache and pref were added in MIPS-III, and MIPS32 but were re-encoded in
MIPS32r6/MIPS64r6 to use a 9-bit offset rather than the 16-bit offset
available to earlier cores.

Resolved the decoding conflict between pref and lwc3.

Depends on D4115

Reviewers: zoran.jovanovic, jkolek, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D4116

llvm-svn: 210900

2014-06-13 13:15:59 +00:00

..

invalid-mips64r2.s

[mips] Fold FeatureSwap into FeatureMips32r2 and FeatureMips64r2

2014-05-12 12:15:41 +00:00

invalid.s

[mips] Implement jr.hb and jalr.hb (Jump Register and Jump and Link Register with Hazard Barrier).

2014-06-11 15:05:56 +00:00

valid-xfail.s

[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS.

2014-05-08 15:17:29 +00:00

valid.s

[mips] Add cache and pref instructions

2014-06-13 13:15:59 +00:00