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More SPU Instructions: Floating point comparison

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* Implemented Floating/Double-floating comparison instructions:
FCGT, FCMGT, FCEQ, FCMEQ, DFCGT, DFCMGT, DFCEQ, DFCMEQ

* Implemented more Floating/Double-floating operations:
FMA, FMS, FNMS, DFMA, DFMS, DFNMS, DFNMA

* Implemented Double / Single floating-point conversion:
FESD, FRSD
This commit is contained in:
Alexandro Sánchez Bach 2013-09-23 12:48:27 +02:00
parent db7e68d308
commit 03dcfeabc3
1 changed files with 62 additions and 17 deletions
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79
rpcs3/Emu/Cell/SPUInterpreter.h
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@ -674,11 +674,13 @@ private:
} }
void FCGT(u32 rt, u32 ra, u32 rb) void FCGT(u32 rt, u32 ra, u32 rb)
{ {
UNIMPLEMENTED(); for (int w = 0; w < 4; w++)
CPU.GPR[rt]._u32[w] = *(float*)&CPU.GPR[ra]._u32[w] > *(float*)&CPU.GPR[rb]._u32[w] ? 0xffffffff : 0;
} }
void DFCGT(u32 rt, u32 ra, u32 rb) void DFCGT(u32 rt, u32 ra, u32 rb)
{ {
UNIMPLEMENTED(); for (int w = 0; w < 2; w++)
CPU.GPR[rt]._u64[w] = *(double*)&CPU.GPR[ra]._u64[w] > *(float*)&CPU.GPR[rb]._u64[w] ? 0xffffffffffffffff : 0;
} }
void FA(u32 rt, u32 ra, u32 rb) void FA(u32 rt, u32 ra, u32 rb)
{ {
@ -716,11 +718,13 @@ private:
} }
void FCMGT(u32 rt, u32 ra, u32 rb) void FCMGT(u32 rt, u32 ra, u32 rb)
{ {
UNIMPLEMENTED(); for (int w = 0; w < 4; w++)
CPU.GPR[rt]._u32[w] = fabs(*(float*)&CPU.GPR[ra]._u32[w]) > fabs(*(float*)&CPU.GPR[rb]._u32[w]) ? 0xffffffff : 0;
} }
void DFCMGT(u32 rt, u32 ra, u32 rb) void DFCMGT(u32 rt, u32 ra, u32 rb)
{ {
UNIMPLEMENTED(); for (int w = 0; w < 2; w++)
CPU.GPR[rt]._u64[w] = fabs(*(double*)&CPU.GPR[ra]._u64[w]) > fabs(*(float*)&CPU.GPR[rb]._u64[w]) ? 0xffffffffffffffff : 0;
} }
void DFA(u32 rt, u32 ra, u32 rb) void DFA(u32 rt, u32 ra, u32 rb)
{ {
@ -757,19 +761,35 @@ private:
} }
void DFMA(u32 rt, u32 ra, u32 rb) void DFMA(u32 rt, u32 ra, u32 rb)
{ {
UNIMPLEMENTED(); for (int w = 0; w < 2; w++)
{
double d = *(double*)&CPU.GPR[ra]._u64[w] * *(double*)&CPU.GPR[rb]._u64[w] + *(double*)&CPU.GPR[rt]._u64[w];
CPU.GPR[rt]._u64[w] = *(u64*)&d;
}
} }
void DFMS(u32 rt, u32 ra, u32 rb) void DFMS(u32 rt, u32 ra, u32 rb)
{ {
UNIMPLEMENTED(); for (int w = 0; w < 2; w++)
{
double d = *(double*)&CPU.GPR[ra]._u64[w] * *(double*)&CPU.GPR[rb]._u64[w] - *(double*)&CPU.GPR[rt]._u64[w];
CPU.GPR[rt]._u64[w] = *(u64*)&d;
}
} }
void DFNMS(u32 rt, u32 ra, u32 rb) void DFNMS(u32 rt, u32 ra, u32 rb)
{ {
UNIMPLEMENTED(); for (int w = 0; w < 2; w++)
{
double d = *(double*)&CPU.GPR[rt]._u64[w] - *(double*)&CPU.GPR[ra]._u64[w] * *(double*)&CPU.GPR[rb]._u64[w];
CPU.GPR[rt]._u64[w] = *(u64*)&d;
}
} }
void DFNMA(u32 rt, u32 ra, u32 rb) void DFNMA(u32 rt, u32 ra, u32 rb)
{ {
UNIMPLEMENTED(); for (int w = 0; w < 2; w++)
{
double d = - *(double*)&CPU.GPR[ra]._u64[w] * *(double*)&CPU.GPR[rb]._u64[w] - *(double*)&CPU.GPR[rt]._u64[w];
CPU.GPR[rt]._u64[w] = *(u64*)&d;
}
} }
void CEQ(u32 rt, u32 ra, u32 rb) void CEQ(u32 rt, u32 ra, u32 rb)
{ {
@ -822,11 +842,20 @@ private:
} }
void FESD(u32 rt, u32 ra) void FESD(u32 rt, u32 ra)
{ {
UNIMPLEMENTED(); for (int w = 0; w < 2; w++)
{
double d = *(float*)&CPU.GPR[ra]._u32[w*2];
CPU.GPR[rt]._u64[w] = *(u64*)&d;
}
} }
void FRDS(u32 rt, u32 ra) void FRDS(u32 rt, u32 ra)
{ {
UNIMPLEMENTED(); for (int w = 0; w < 2; w++)
{
float f = *(double*)&CPU.GPR[ra]._u64[w];
CPU.GPR[rt]._u32[w*2] = *(u32*)&f;
CPU.GPR[rt]._u32[w*2+1] = 0x00000000;
}
} }
void FSCRWR(u32 rt, u32 ra) void FSCRWR(u32 rt, u32 ra)
{ {
@ -838,11 +867,13 @@ private:
} }
void FCEQ(u32 rt, u32 ra, u32 rb) void FCEQ(u32 rt, u32 ra, u32 rb)
{ {
UNIMPLEMENTED(); for (int w = 0; w < 4; w++)
CPU.GPR[rt]._u32[w] = *(float*)&CPU.GPR[ra]._u32[w] == *(float*)&CPU.GPR[rb]._u32[w] ? 0xffffffff : 0;
} }
void DFCEQ(u32 rt, u32 ra, u32 rb) void DFCEQ(u32 rt, u32 ra, u32 rb)
{ {
UNIMPLEMENTED(); for (int w = 0; w < 2; w++)
CPU.GPR[rt]._u64[w] = *(double*)&CPU.GPR[ra]._u64[w] == *(float*)&CPU.GPR[rb]._u64[w] ? 0xffffffffffffffff : 0;
} }
void MPY(u32 rt, u32 ra, u32 rb) void MPY(u32 rt, u32 ra, u32 rb)
{ {
@ -871,11 +902,13 @@ private:
} }
void FCMEQ(u32 rt, u32 ra, u32 rb) void FCMEQ(u32 rt, u32 ra, u32 rb)
{ {
UNIMPLEMENTED(); for (int w = 0; w < 4; w++)
CPU.GPR[rt]._u32[w] = fabs(*(float*)&CPU.GPR[ra]._u32[w]) == fabs(*(float*)&CPU.GPR[rb]._u32[w]) ? 0xffffffff : 0;
} }
void DFCMEQ(u32 rt, u32 ra, u32 rb) void DFCMEQ(u32 rt, u32 ra, u32 rb)
{ {
UNIMPLEMENTED(); for (int w = 0; w < 2; w++)
CPU.GPR[rt]._u64[w] = fabs(*(double*)&CPU.GPR[ra]._u64[w]) > fabs(*(float*)&CPU.GPR[rb]._u64[w]) ? 0xffffffffffffffff : 0;
} }
void MPYU(u32 rt, u32 ra, u32 rb) void MPYU(u32 rt, u32 ra, u32 rb)
{ {
@ -1201,15 +1234,27 @@ private:
} }
void FNMS(u32 rt, u32 ra, u32 rb, u32 rc) void FNMS(u32 rt, u32 ra, u32 rb, u32 rc)
{ {
UNIMPLEMENTED(); for (int w = 0; w < 4; w++)
{
float f = *(float*)&CPU.GPR[rc]._u32[w] - *(float*)&CPU.GPR[ra]._u32[w] * *(float*)&CPU.GPR[rb]._u32[w];
CPU.GPR[rt]._u32[w] = *(u32*)&f;
}
} }
void FMA(u32 rc, u32 ra, u32 rb, u32 rt) void FMA(u32 rc, u32 ra, u32 rb, u32 rt)
{ {
UNIMPLEMENTED(); for (int w = 0; w < 4; w++)
{
float f = *(float*)&CPU.GPR[ra]._u32[w] * *(float*)&CPU.GPR[rb]._u32[w] + *(float*)&CPU.GPR[rc]._u32[w];
CPU.GPR[rt]._u32[w] = *(u32*)&f;
}
} }
void FMS(u32 rc, u32 ra, u32 rb, u32 rt) void FMS(u32 rc, u32 ra, u32 rb, u32 rt)
{ {
UNIMPLEMENTED(); for (int w = 0; w < 4; w++)
{
float f = *(float*)&CPU.GPR[ra]._u32[w] * *(float*)&CPU.GPR[rb]._u32[w] - *(float*)&CPU.GPR[rc]._u32[w];
CPU.GPR[rt]._u32[w] = *(u32*)&f;
}
} }
void UNK(u32 code, u32 opcode, u32 gcode) void UNK(u32 code, u32 opcode, u32 gcode)