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SPR removed from SPU
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parent
64935ccee6
commit
55ee7065be
@ -61,17 +61,6 @@ private:
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void MFSPR(u32 rt, u32 sa)
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{
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UNIMPLEMENTED();
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//If register is a dummy register (register labeled 0x0)
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if(sa == 0x0)
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{
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CPU.GPR[rt]._u128.hi = 0x0;
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CPU.GPR[rt]._u128.lo = 0x0;
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}
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else
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{
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CPU.GPR[rt]._u128.hi = CPU.SPR[sa]._u128.hi;
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CPU.GPR[rt]._u128.lo = CPU.SPR[sa]._u128.lo;
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}
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}
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void RDCH(u32 rt, u32 ra)
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{
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@ -267,11 +256,7 @@ private:
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}
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void MTSPR(u32 rt, u32 sa)
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{
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if(sa != 0)
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{
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CPU.SPR[sa]._u128.hi = CPU.GPR[rt]._u128.hi;
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CPU.SPR[sa]._u128.lo = CPU.GPR[rt]._u128.lo;
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}
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UNIMPLEMENTED();
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}
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void WRCH(u32 ra, u32 rt)
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{
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@ -471,17 +471,6 @@ private:
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void MFSPR(u32 rt, u32 sa)
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{
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UNIMPLEMENTED();
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//If register is a dummy register (register labeled 0x0)
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if(sa == 0x0)
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{
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CPU.GPR[rt]._u128.hi = 0x0;
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CPU.GPR[rt]._u128.lo = 0x0;
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}
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else
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{
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CPU.GPR[rt]._u128.hi = CPU.SPR[sa]._u128.hi;
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CPU.GPR[rt]._u128.lo = CPU.SPR[sa]._u128.lo;
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}
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}
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void RDCH(u32 rt, u32 ra)
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{
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@ -1098,11 +1087,6 @@ private:
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void MTSPR(u32 rt, u32 sa)
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{
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UNIMPLEMENTED();
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if(sa != 0)
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{
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CPU.SPR[sa]._u128.hi = CPU.GPR[rt]._u128.hi;
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CPU.SPR[sa]._u128.lo = CPU.GPR[rt]._u128.lo;
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}
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}
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void WRCH(u32 ra, u32 rt)
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{
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@ -310,8 +310,7 @@ union SPU_SNRConfig_hdr
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class SPUThread : public PPCThread
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{
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public:
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SPU_GPR_hdr GPR[128]; //General-Purpose Register
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SPU_SPR_hdr SPR[128]; //Special-Purpose Registers
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SPU_GPR_hdr GPR[128]; //General-Purpose Registers
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//FPSCR FPSCR;
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SPU_SNRConfig_hdr cfg; //Signal Notification Registers Configuration (OR-mode enabled: 0x1 for SNR1, 0x2 for SNR2)
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