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llvm-mirror/test/CodeGen/AArch64/strpre-str-merge.mir

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[AArch64] Adds a pre-indexed paired Load/Store optimization for LDR-STR. This patch merges STR<S,D,Q,W,X>pre-STR<S,D,Q,W,X>ui and LDR<S,D,Q,W,X>pre-LDR<S,D,Q,W,X>ui instruction pairs into a single STP<S,D,Q,W,X>pre and LDP<S,D,Q,W,X>pre instruction, respectively. For each pair, there is a MIR test that verifies this optimization. Differential Revision: https://reviews.llvm.org/D99272 Change-Id: Ie97a20c8c716c08492fe229c22e14e3c98ef08b7
2021-04-30 17:19:48 +02:00
# RUN: llc -o - %s -mtriple=aarch64-none-eabi -mcpu=cortex-a55 -lsr-preferred-addressing-mode=preindexed -stop-after=aarch64-ldst-opt | FileCheck %s
---
name: 1-strwpre-strwui-merge
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
- { reg: '$w1' }
- { reg: '$w2' }
frameInfo:
maxAlignment: 1
maxCallFrameSize: 0
machineFunctionInfo:
hasRedZone: false
body: |
bb.0.entry:
liveins: $w1, $w2, $x0
; CHECK-LABEL: name: 1-strwpre-strwui-merge
; CHECK: liveins: $w1, $w2, $x0
CodeGen: Print/parse LLTs in MachineMemOperands This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
2021-05-20 04:25:51 +02:00
; CHECK: early-clobber $x0 = STPWpre renamable $w1, renamable $w2, renamable $x0, 5 :: (store (s32))
[AArch64] Adds a pre-indexed paired Load/Store optimization for LDR-STR. This patch merges STR<S,D,Q,W,X>pre-STR<S,D,Q,W,X>ui and LDR<S,D,Q,W,X>pre-LDR<S,D,Q,W,X>ui instruction pairs into a single STP<S,D,Q,W,X>pre and LDP<S,D,Q,W,X>pre instruction, respectively. For each pair, there is a MIR test that verifies this optimization. Differential Revision: https://reviews.llvm.org/D99272 Change-Id: Ie97a20c8c716c08492fe229c22e14e3c98ef08b7
2021-04-30 17:19:48 +02:00
; CHECK: RET undef $lr, implicit $x0
CodeGen: Print/parse LLTs in MachineMemOperands This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
2021-05-20 04:25:51 +02:00
early-clobber renamable $x0 = STRWpre killed renamable $w1, killed renamable $x0, 20 :: (store (s32))
STRWui killed renamable $w2, renamable $x0, 1 :: (store (s32))
[AArch64] Adds a pre-indexed paired Load/Store optimization for LDR-STR. This patch merges STR<S,D,Q,W,X>pre-STR<S,D,Q,W,X>ui and LDR<S,D,Q,W,X>pre-LDR<S,D,Q,W,X>ui instruction pairs into a single STP<S,D,Q,W,X>pre and LDP<S,D,Q,W,X>pre instruction, respectively. For each pair, there is a MIR test that verifies this optimization. Differential Revision: https://reviews.llvm.org/D99272 Change-Id: Ie97a20c8c716c08492fe229c22e14e3c98ef08b7
2021-04-30 17:19:48 +02:00
RET undef $lr, implicit $x0
...
---
name: 2-strxpre-strxui-merge
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
- { reg: '$x1' }
- { reg: '$x2' }
frameInfo:
maxAlignment: 1
maxCallFrameSize: 0
machineFunctionInfo:
hasRedZone: false
body: |
bb.0.entry:
liveins: $x0, $x1, $x2
; CHECK-LABEL: name: 2-strxpre-strxui-merge
; CHECK: liveins: $x0, $x1, $x2
CodeGen: Print/parse LLTs in MachineMemOperands This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
2021-05-20 04:25:51 +02:00
; CHECK: early-clobber $x0 = STPXpre renamable $x1, renamable $x2, renamable $x0, 3 :: (store (s64))
[AArch64] Adds a pre-indexed paired Load/Store optimization for LDR-STR. This patch merges STR<S,D,Q,W,X>pre-STR<S,D,Q,W,X>ui and LDR<S,D,Q,W,X>pre-LDR<S,D,Q,W,X>ui instruction pairs into a single STP<S,D,Q,W,X>pre and LDP<S,D,Q,W,X>pre instruction, respectively. For each pair, there is a MIR test that verifies this optimization. Differential Revision: https://reviews.llvm.org/D99272 Change-Id: Ie97a20c8c716c08492fe229c22e14e3c98ef08b7
2021-04-30 17:19:48 +02:00
; CHECK: RET undef $lr, implicit $x0
CodeGen: Print/parse LLTs in MachineMemOperands This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
2021-05-20 04:25:51 +02:00
early-clobber renamable $x0 = STRXpre killed renamable $x1, killed renamable $x0, 24 :: (store (s64))
STRXui killed renamable $x2, renamable $x0, 1 :: (store (s64))
[AArch64] Adds a pre-indexed paired Load/Store optimization for LDR-STR. This patch merges STR<S,D,Q,W,X>pre-STR<S,D,Q,W,X>ui and LDR<S,D,Q,W,X>pre-LDR<S,D,Q,W,X>ui instruction pairs into a single STP<S,D,Q,W,X>pre and LDP<S,D,Q,W,X>pre instruction, respectively. For each pair, there is a MIR test that verifies this optimization. Differential Revision: https://reviews.llvm.org/D99272 Change-Id: Ie97a20c8c716c08492fe229c22e14e3c98ef08b7
2021-04-30 17:19:48 +02:00
RET undef $lr, implicit $x0
...
---
name: 3-strspre-strsui-merge
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
- { reg: '$s0' }
- { reg: '$s1' }
frameInfo:
maxAlignment: 1
maxCallFrameSize: 0
machineFunctionInfo:
hasRedZone: false
body: |
bb.0.entry:
liveins: $s0, $s1, $x0
; CHECK-LABEL: name: 3-strspre-strsui-merge
; CHECK: liveins: $s0, $s1, $x0
CodeGen: Print/parse LLTs in MachineMemOperands This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
2021-05-20 04:25:51 +02:00
; CHECK: early-clobber $x0 = STPSpre renamable $s0, renamable $s1, renamable $x0, 3 :: (store (s32))
[AArch64] Adds a pre-indexed paired Load/Store optimization for LDR-STR. This patch merges STR<S,D,Q,W,X>pre-STR<S,D,Q,W,X>ui and LDR<S,D,Q,W,X>pre-LDR<S,D,Q,W,X>ui instruction pairs into a single STP<S,D,Q,W,X>pre and LDP<S,D,Q,W,X>pre instruction, respectively. For each pair, there is a MIR test that verifies this optimization. Differential Revision: https://reviews.llvm.org/D99272 Change-Id: Ie97a20c8c716c08492fe229c22e14e3c98ef08b7
2021-04-30 17:19:48 +02:00
; CHECK: RET undef $lr, implicit $x0
CodeGen: Print/parse LLTs in MachineMemOperands This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
2021-05-20 04:25:51 +02:00
early-clobber renamable $x0 = STRSpre killed renamable $s0, killed renamable $x0, 12 :: (store (s32))
STRSui killed renamable $s1, renamable $x0, 1 :: (store (s32))
[AArch64] Adds a pre-indexed paired Load/Store optimization for LDR-STR. This patch merges STR<S,D,Q,W,X>pre-STR<S,D,Q,W,X>ui and LDR<S,D,Q,W,X>pre-LDR<S,D,Q,W,X>ui instruction pairs into a single STP<S,D,Q,W,X>pre and LDP<S,D,Q,W,X>pre instruction, respectively. For each pair, there is a MIR test that verifies this optimization. Differential Revision: https://reviews.llvm.org/D99272 Change-Id: Ie97a20c8c716c08492fe229c22e14e3c98ef08b7
2021-04-30 17:19:48 +02:00
RET undef $lr, implicit $x0
...
---
name: 4-strdpre-strdui-merge
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
- { reg: '$d0' }
- { reg: '$d1' }
frameInfo:
maxAlignment: 1
maxCallFrameSize: 0
machineFunctionInfo:
hasRedZone: false
body: |
bb.0.entry:
liveins: $d0, $d1, $x0
; CHECK-LABEL: name: 4-strdpre-strdui-merge
; CHECK: liveins: $d0, $d1, $x0
CodeGen: Print/parse LLTs in MachineMemOperands This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
2021-05-20 04:25:51 +02:00
; CHECK: early-clobber $x0 = STPDpre renamable $d0, renamable $d1, renamable $x0, 16 :: (store (s64))
[AArch64] Adds a pre-indexed paired Load/Store optimization for LDR-STR. This patch merges STR<S,D,Q,W,X>pre-STR<S,D,Q,W,X>ui and LDR<S,D,Q,W,X>pre-LDR<S,D,Q,W,X>ui instruction pairs into a single STP<S,D,Q,W,X>pre and LDP<S,D,Q,W,X>pre instruction, respectively. For each pair, there is a MIR test that verifies this optimization. Differential Revision: https://reviews.llvm.org/D99272 Change-Id: Ie97a20c8c716c08492fe229c22e14e3c98ef08b7
2021-04-30 17:19:48 +02:00
; CHECK: RET undef $lr, implicit $x0
CodeGen: Print/parse LLTs in MachineMemOperands This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
2021-05-20 04:25:51 +02:00
early-clobber renamable $x0 = STRDpre killed renamable $d0, killed renamable $x0, 128 :: (store (s64))
STRDui killed renamable $d1, renamable $x0, 1 :: (store (s64))
[AArch64] Adds a pre-indexed paired Load/Store optimization for LDR-STR. This patch merges STR<S,D,Q,W,X>pre-STR<S,D,Q,W,X>ui and LDR<S,D,Q,W,X>pre-LDR<S,D,Q,W,X>ui instruction pairs into a single STP<S,D,Q,W,X>pre and LDP<S,D,Q,W,X>pre instruction, respectively. For each pair, there is a MIR test that verifies this optimization. Differential Revision: https://reviews.llvm.org/D99272 Change-Id: Ie97a20c8c716c08492fe229c22e14e3c98ef08b7
2021-04-30 17:19:48 +02:00
RET undef $lr, implicit $x0
...
---
name: 5-strqpre-strqui-merge
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
- { reg: '$q0' }
- { reg: '$q1' }
frameInfo:
maxAlignment: 1
maxCallFrameSize: 0
machineFunctionInfo:
hasRedZone: false
body: |
bb.0.entry:
liveins: $q0, $q1, $x0
; CHECK-LABEL: name: 5-strqpre-strqui-merge
; CHECK: liveins: $q0, $q1, $x0
CodeGen: Print/parse LLTs in MachineMemOperands This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
2021-05-20 04:25:51 +02:00
; CHECK: early-clobber $x0 = STPQpre renamable $q0, renamable $q1, renamable $x0, 3 :: (store (s128))
[AArch64] Adds a pre-indexed paired Load/Store optimization for LDR-STR. This patch merges STR<S,D,Q,W,X>pre-STR<S,D,Q,W,X>ui and LDR<S,D,Q,W,X>pre-LDR<S,D,Q,W,X>ui instruction pairs into a single STP<S,D,Q,W,X>pre and LDP<S,D,Q,W,X>pre instruction, respectively. For each pair, there is a MIR test that verifies this optimization. Differential Revision: https://reviews.llvm.org/D99272 Change-Id: Ie97a20c8c716c08492fe229c22e14e3c98ef08b7
2021-04-30 17:19:48 +02:00
; CHECK: RET undef $lr, implicit $x0
CodeGen: Print/parse LLTs in MachineMemOperands This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
2021-05-20 04:25:51 +02:00
early-clobber renamable $x0 = STRQpre killed renamable $q0, killed renamable $x0, 48 :: (store (s128))
STRQui killed renamable $q1, renamable $x0, 1 :: (store (s128))
[AArch64] Adds a pre-indexed paired Load/Store optimization for LDR-STR. This patch merges STR<S,D,Q,W,X>pre-STR<S,D,Q,W,X>ui and LDR<S,D,Q,W,X>pre-LDR<S,D,Q,W,X>ui instruction pairs into a single STP<S,D,Q,W,X>pre and LDP<S,D,Q,W,X>pre instruction, respectively. For each pair, there is a MIR test that verifies this optimization. Differential Revision: https://reviews.llvm.org/D99272 Change-Id: Ie97a20c8c716c08492fe229c22e14e3c98ef08b7
2021-04-30 17:19:48 +02:00
RET undef $lr, implicit $x0
...
---
name: 6-strqui-strqpre-no-merge
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
- { reg: '$q0' }
- { reg: '$q1' }
frameInfo:
maxAlignment: 1
maxCallFrameSize: 0
machineFunctionInfo:
hasRedZone: false
body: |
bb.0.entry:
liveins: $q0, $q1, $x0
; CHECK-LABEL: name: 6-strqui-strqpre-no-merge
; CHECK: liveins: $q0, $q1, $x0
CodeGen: Print/parse LLTs in MachineMemOperands This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
2021-05-20 04:25:51 +02:00
; CHECK: STRQui renamable $q1, renamable $x0, 1 :: (store (s128))
; CHECK: early-clobber renamable $x0 = STRQpre renamable $q0, renamable $x0, 48, implicit $w0 :: (store (s128))
[AArch64] Adds a pre-indexed paired Load/Store optimization for LDR-STR. This patch merges STR<S,D,Q,W,X>pre-STR<S,D,Q,W,X>ui and LDR<S,D,Q,W,X>pre-LDR<S,D,Q,W,X>ui instruction pairs into a single STP<S,D,Q,W,X>pre and LDP<S,D,Q,W,X>pre instruction, respectively. For each pair, there is a MIR test that verifies this optimization. Differential Revision: https://reviews.llvm.org/D99272 Change-Id: Ie97a20c8c716c08492fe229c22e14e3c98ef08b7
2021-04-30 17:19:48 +02:00
; CHECK: RET undef $lr, implicit $x0
CodeGen: Print/parse LLTs in MachineMemOperands This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
2021-05-20 04:25:51 +02:00
STRQui killed renamable $q1, renamable $x0, 1 :: (store (s128))
early-clobber renamable $x0 = STRQpre killed renamable $q0, killed renamable $x0, 48 :: (store (s128))
[AArch64] Adds a pre-indexed paired Load/Store optimization for LDR-STR. This patch merges STR<S,D,Q,W,X>pre-STR<S,D,Q,W,X>ui and LDR<S,D,Q,W,X>pre-LDR<S,D,Q,W,X>ui instruction pairs into a single STP<S,D,Q,W,X>pre and LDP<S,D,Q,W,X>pre instruction, respectively. For each pair, there is a MIR test that verifies this optimization. Differential Revision: https://reviews.llvm.org/D99272 Change-Id: Ie97a20c8c716c08492fe229c22e14e3c98ef08b7
2021-04-30 17:19:48 +02:00
RET undef $lr, implicit $x0
...
---
name: 7-strspre-strsui-max-offset-merge
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
- { reg: '$s0' }
- { reg: '$s1' }
frameInfo:
maxAlignment: 1
maxCallFrameSize: 0
machineFunctionInfo:
hasRedZone: false
body: |
bb.0.entry:
liveins: $s0, $s1, $x0
; CHECK-LABEL: name: 7-strspre-strsui-max-offset-merge
; CHECK: liveins: $s0, $s1, $x0
CodeGen: Print/parse LLTs in MachineMemOperands This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
2021-05-20 04:25:51 +02:00
; CHECK: early-clobber $x0 = STPSpre renamable $s0, renamable $s1, renamable $x0, 63 :: (store (s32))
[AArch64] Adds a pre-indexed paired Load/Store optimization for LDR-STR. This patch merges STR<S,D,Q,W,X>pre-STR<S,D,Q,W,X>ui and LDR<S,D,Q,W,X>pre-LDR<S,D,Q,W,X>ui instruction pairs into a single STP<S,D,Q,W,X>pre and LDP<S,D,Q,W,X>pre instruction, respectively. For each pair, there is a MIR test that verifies this optimization. Differential Revision: https://reviews.llvm.org/D99272 Change-Id: Ie97a20c8c716c08492fe229c22e14e3c98ef08b7
2021-04-30 17:19:48 +02:00
; CHECK: RET undef $lr, implicit $x0
CodeGen: Print/parse LLTs in MachineMemOperands This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
2021-05-20 04:25:51 +02:00
early-clobber renamable $x0 = STRSpre killed renamable $s0, killed renamable $x0, 252 :: (store (s32))
STRSui killed renamable $s1, renamable $x0, 1 :: (store (s32))
[AArch64] Adds a pre-indexed paired Load/Store optimization for LDR-STR. This patch merges STR<S,D,Q,W,X>pre-STR<S,D,Q,W,X>ui and LDR<S,D,Q,W,X>pre-LDR<S,D,Q,W,X>ui instruction pairs into a single STP<S,D,Q,W,X>pre and LDP<S,D,Q,W,X>pre instruction, respectively. For each pair, there is a MIR test that verifies this optimization. Differential Revision: https://reviews.llvm.org/D99272 Change-Id: Ie97a20c8c716c08492fe229c22e14e3c98ef08b7
2021-04-30 17:19:48 +02:00
RET undef $lr, implicit $x0
...
---
name: 8-strspre-strsui-min-offset-merge
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
- { reg: '$s0' }
- { reg: '$s1' }
frameInfo:
maxAlignment: 1
maxCallFrameSize: 0
machineFunctionInfo:
hasRedZone: false
body: |
bb.0.entry:
liveins: $s0, $s1, $x0
; CHECK-LABEL: name: 8-strspre-strsui-min-offset-merge
; CHECK: liveins: $s0, $s1, $x0
CodeGen: Print/parse LLTs in MachineMemOperands This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
2021-05-20 04:25:51 +02:00
; CHECK: early-clobber $x0 = STPSpre renamable $s0, renamable $s1, renamable $x0, -64 :: (store (s32))
[AArch64] Adds a pre-indexed paired Load/Store optimization for LDR-STR. This patch merges STR<S,D,Q,W,X>pre-STR<S,D,Q,W,X>ui and LDR<S,D,Q,W,X>pre-LDR<S,D,Q,W,X>ui instruction pairs into a single STP<S,D,Q,W,X>pre and LDP<S,D,Q,W,X>pre instruction, respectively. For each pair, there is a MIR test that verifies this optimization. Differential Revision: https://reviews.llvm.org/D99272 Change-Id: Ie97a20c8c716c08492fe229c22e14e3c98ef08b7
2021-04-30 17:19:48 +02:00
; CHECK: RET undef $lr, implicit $x0
CodeGen: Print/parse LLTs in MachineMemOperands This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
2021-05-20 04:25:51 +02:00
early-clobber renamable $x0 = STRSpre killed renamable $s0, killed renamable $x0, -256 :: (store (s32))
STRSui killed renamable $s1, renamable $x0, 1 :: (store (s32))
[AArch64] Adds a pre-indexed paired Load/Store optimization for LDR-STR. This patch merges STR<S,D,Q,W,X>pre-STR<S,D,Q,W,X>ui and LDR<S,D,Q,W,X>pre-LDR<S,D,Q,W,X>ui instruction pairs into a single STP<S,D,Q,W,X>pre and LDP<S,D,Q,W,X>pre instruction, respectively. For each pair, there is a MIR test that verifies this optimization. Differential Revision: https://reviews.llvm.org/D99272 Change-Id: Ie97a20c8c716c08492fe229c22e14e3c98ef08b7
2021-04-30 17:19:48 +02:00
RET undef $lr, implicit $x0
...
---
name: 9-strspre-strsui-mod-base-reg-no-merge
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
- { reg: '$x1' }
- { reg: '$s0' }
- { reg: '$s1' }
frameInfo:
maxAlignment: 1
maxCallFrameSize: 0
machineFunctionInfo:
hasRedZone: false
body: |
bb.0.entry:
liveins: $s0, $s1, $x0, $x1
; CHECK-LABEL: name: 9-strspre-strsui-mod-base-reg-no-merge
; CHECK: liveins: $s0, $s1, $x0, $x1
CodeGen: Print/parse LLTs in MachineMemOperands This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
2021-05-20 04:25:51 +02:00
; CHECK: dead early-clobber renamable $x0 = STRSpre renamable $s0, renamable $x0, 12, implicit $w0 :: (store (s32))
; CHECK: renamable $x0 = LDRXui renamable $x1, 1 :: (load (s64))
; CHECK: STRSui renamable $s1, renamable $x0, 1 :: (store (s32))
[AArch64] Adds a pre-indexed paired Load/Store optimization for LDR-STR. This patch merges STR<S,D,Q,W,X>pre-STR<S,D,Q,W,X>ui and LDR<S,D,Q,W,X>pre-LDR<S,D,Q,W,X>ui instruction pairs into a single STP<S,D,Q,W,X>pre and LDP<S,D,Q,W,X>pre instruction, respectively. For each pair, there is a MIR test that verifies this optimization. Differential Revision: https://reviews.llvm.org/D99272 Change-Id: Ie97a20c8c716c08492fe229c22e14e3c98ef08b7
2021-04-30 17:19:48 +02:00
; CHECK: RET undef $lr, implicit $x0
CodeGen: Print/parse LLTs in MachineMemOperands This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
2021-05-20 04:25:51 +02:00
early-clobber renamable $x0 = STRSpre killed renamable $s0, killed renamable $x0, 12 :: (store (s32))
renamable $x0 = LDRXui renamable $x1, 1 :: (load (s64))
STRSui killed renamable $s1, renamable $x0, 1 :: (store (s32))
[AArch64] Adds a pre-indexed paired Load/Store optimization for LDR-STR. This patch merges STR<S,D,Q,W,X>pre-STR<S,D,Q,W,X>ui and LDR<S,D,Q,W,X>pre-LDR<S,D,Q,W,X>ui instruction pairs into a single STP<S,D,Q,W,X>pre and LDP<S,D,Q,W,X>pre instruction, respectively. For each pair, there is a MIR test that verifies this optimization. Differential Revision: https://reviews.llvm.org/D99272 Change-Id: Ie97a20c8c716c08492fe229c22e14e3c98ef08b7
2021-04-30 17:19:48 +02:00
RET undef $lr, implicit $x0
...
---
name: 10-strspre-strsui-used-base-reg-no-merge
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
- { reg: '$x1' }
- { reg: '$s0' }
- { reg: '$s1' }
frameInfo:
maxAlignment: 1
maxCallFrameSize: 0
machineFunctionInfo:
hasRedZone: false
body: |
bb.0.entry:
liveins: $s0, $s1, $x0, $x1
; CHECK-LABEL: name: 10-strspre-strsui-used-base-reg-no-merge
; CHECK: liveins: $s0, $s1, $x0, $x1
CodeGen: Print/parse LLTs in MachineMemOperands This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
2021-05-20 04:25:51 +02:00
; CHECK: early-clobber renamable $x0 = STRSpre renamable $s0, renamable $x0, 12, implicit $w0 :: (store (s32))
; CHECK: STRXui renamable $x1, renamable $x1, 1 :: (store (s32))
; CHECK: STRSui renamable $s1, renamable $x0, 1 :: (store (s32))
[AArch64] Adds a pre-indexed paired Load/Store optimization for LDR-STR. This patch merges STR<S,D,Q,W,X>pre-STR<S,D,Q,W,X>ui and LDR<S,D,Q,W,X>pre-LDR<S,D,Q,W,X>ui instruction pairs into a single STP<S,D,Q,W,X>pre and LDP<S,D,Q,W,X>pre instruction, respectively. For each pair, there is a MIR test that verifies this optimization. Differential Revision: https://reviews.llvm.org/D99272 Change-Id: Ie97a20c8c716c08492fe229c22e14e3c98ef08b7
2021-04-30 17:19:48 +02:00
; CHECK: RET undef $lr, implicit $x0
CodeGen: Print/parse LLTs in MachineMemOperands This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
2021-05-20 04:25:51 +02:00
early-clobber renamable $x0 = STRSpre killed renamable $s0, killed renamable $x0, 12 :: (store (s32))
[AArch64] Adds a pre-indexed paired Load/Store optimization for LDR-STR. This patch merges STR<S,D,Q,W,X>pre-STR<S,D,Q,W,X>ui and LDR<S,D,Q,W,X>pre-LDR<S,D,Q,W,X>ui instruction pairs into a single STP<S,D,Q,W,X>pre and LDP<S,D,Q,W,X>pre instruction, respectively. For each pair, there is a MIR test that verifies this optimization. Differential Revision: https://reviews.llvm.org/D99272 Change-Id: Ie97a20c8c716c08492fe229c22e14e3c98ef08b7
2021-04-30 17:19:48 +02:00
CodeGen: Print/parse LLTs in MachineMemOperands This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
2021-05-20 04:25:51 +02:00
STRXui killed renamable $x1, renamable $x1, 1 :: (store (s32))
[AArch64] Adds a pre-indexed paired Load/Store optimization for LDR-STR. This patch merges STR<S,D,Q,W,X>pre-STR<S,D,Q,W,X>ui and LDR<S,D,Q,W,X>pre-LDR<S,D,Q,W,X>ui instruction pairs into a single STP<S,D,Q,W,X>pre and LDP<S,D,Q,W,X>pre instruction, respectively. For each pair, there is a MIR test that verifies this optimization. Differential Revision: https://reviews.llvm.org/D99272 Change-Id: Ie97a20c8c716c08492fe229c22e14e3c98ef08b7
2021-04-30 17:19:48 +02:00
CodeGen: Print/parse LLTs in MachineMemOperands This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
2021-05-20 04:25:51 +02:00
STRSui killed renamable $s1, renamable $x0, 1 :: (store (s32))
[AArch64] Adds a pre-indexed paired Load/Store optimization for LDR-STR. This patch merges STR<S,D,Q,W,X>pre-STR<S,D,Q,W,X>ui and LDR<S,D,Q,W,X>pre-LDR<S,D,Q,W,X>ui instruction pairs into a single STP<S,D,Q,W,X>pre and LDP<S,D,Q,W,X>pre instruction, respectively. For each pair, there is a MIR test that verifies this optimization. Differential Revision: https://reviews.llvm.org/D99272 Change-Id: Ie97a20c8c716c08492fe229c22e14e3c98ef08b7
2021-04-30 17:19:48 +02:00
RET undef $lr, implicit $x0
...
---
name: 11-strspre-strspre-no-merge
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
- { reg: '$s0' }
- { reg: '$s1' }
frameInfo:
maxAlignment: 1
maxCallFrameSize: 0
machineFunctionInfo:
hasRedZone: false
body: |
bb.0.entry:
liveins: $s0, $s1, $x0
; CHECK-LABEL: name: 11-strspre-strspre-no-merge
; CHECK: liveins: $s0, $s1, $x0
CodeGen: Print/parse LLTs in MachineMemOperands This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
2021-05-20 04:25:51 +02:00
; CHECK: early-clobber renamable $x0 = STRSpre renamable $s0, renamable $x0, 12, implicit $w0 :: (store (s32))
; CHECK: early-clobber renamable $x0 = STRSpre renamable $s1, renamable $x0, 16, implicit $w0 :: (store (s32))
; CHECK: early-clobber renamable $x0 = STRSpre renamable $s0, renamable $x0, 4, implicit $w0 :: (store (s32))
; CHECK: early-clobber renamable $x0 = STRSpre renamable $s1, renamable $x0, 12, implicit $w0 :: (store (s32))
; CHECK: early-clobber renamable $x0 = STRSpre renamable $s0, renamable $x0, 4, implicit $w0 :: (store (s32))
; CHECK: early-clobber renamable $x0 = STRSpre renamable $s1, renamable $x0, 4, implicit $w0 :: (store (s32))
[AArch64] Adds a pre-indexed paired Load/Store optimization for LDR-STR. This patch merges STR<S,D,Q,W,X>pre-STR<S,D,Q,W,X>ui and LDR<S,D,Q,W,X>pre-LDR<S,D,Q,W,X>ui instruction pairs into a single STP<S,D,Q,W,X>pre and LDP<S,D,Q,W,X>pre instruction, respectively. For each pair, there is a MIR test that verifies this optimization. Differential Revision: https://reviews.llvm.org/D99272 Change-Id: Ie97a20c8c716c08492fe229c22e14e3c98ef08b7
2021-04-30 17:19:48 +02:00
; CHECK: RET undef $lr, implicit $x0
CodeGen: Print/parse LLTs in MachineMemOperands This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
2021-05-20 04:25:51 +02:00
early-clobber renamable $x0 = STRSpre renamable $s0, killed renamable $x0, 12 :: (store (s32))
early-clobber renamable $x0 = STRSpre renamable $s1, killed renamable $x0, 16 :: (store (s32))
early-clobber renamable $x0 = STRSpre renamable $s0, killed renamable $x0, 4 :: (store (s32))
early-clobber renamable $x0 = STRSpre renamable $s1, killed renamable $x0, 12 :: (store (s32))
early-clobber renamable $x0 = STRSpre renamable $s0, killed renamable $x0, 4 :: (store (s32))
early-clobber renamable $x0 = STRSpre renamable $s1, killed renamable $x0, 4 :: (store (s32))
[AArch64] Adds a pre-indexed paired Load/Store optimization for LDR-STR. This patch merges STR<S,D,Q,W,X>pre-STR<S,D,Q,W,X>ui and LDR<S,D,Q,W,X>pre-LDR<S,D,Q,W,X>ui instruction pairs into a single STP<S,D,Q,W,X>pre and LDP<S,D,Q,W,X>pre instruction, respectively. For each pair, there is a MIR test that verifies this optimization. Differential Revision: https://reviews.llvm.org/D99272 Change-Id: Ie97a20c8c716c08492fe229c22e14e3c98ef08b7
2021-04-30 17:19:48 +02:00
RET undef $lr, implicit $x0
...
---
name: 12-strspre-strsui-no-merge
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
- { reg: '$s0' }
- { reg: '$s1' }
frameInfo:
maxAlignment: 1
maxCallFrameSize: 0
machineFunctionInfo:
hasRedZone: false
body: |
bb.0.entry:
; The offset of the second st is not equal to the
; size of the destination register, and hence can’t be merged.
liveins: $s0, $s1, $x0
; CHECK-LABEL: name: 12-strspre-strsui-no-merge
; CHECK: liveins: $s0, $s1, $x0
CodeGen: Print/parse LLTs in MachineMemOperands This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
2021-05-20 04:25:51 +02:00
; CHECK: early-clobber renamable $x0 = STRSpre renamable $s0, renamable $x0, 12, implicit $w0 :: (store (s32))
; CHECK: STRSui renamable $s1, renamable $x0, 2 :: (store (s32))
[AArch64] Adds a pre-indexed paired Load/Store optimization for LDR-STR. This patch merges STR<S,D,Q,W,X>pre-STR<S,D,Q,W,X>ui and LDR<S,D,Q,W,X>pre-LDR<S,D,Q,W,X>ui instruction pairs into a single STP<S,D,Q,W,X>pre and LDP<S,D,Q,W,X>pre instruction, respectively. For each pair, there is a MIR test that verifies this optimization. Differential Revision: https://reviews.llvm.org/D99272 Change-Id: Ie97a20c8c716c08492fe229c22e14e3c98ef08b7
2021-04-30 17:19:48 +02:00
; CHECK: RET undef $lr, implicit $x0
CodeGen: Print/parse LLTs in MachineMemOperands This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
2021-05-20 04:25:51 +02:00
early-clobber renamable $x0 = STRSpre killed renamable $s0, killed renamable $x0, 12 :: (store (s32))
STRSui killed renamable $s1, renamable $x0, 2 :: (store (s32))
[AArch64] Adds a pre-indexed paired Load/Store optimization for LDR-STR. This patch merges STR<S,D,Q,W,X>pre-STR<S,D,Q,W,X>ui and LDR<S,D,Q,W,X>pre-LDR<S,D,Q,W,X>ui instruction pairs into a single STP<S,D,Q,W,X>pre and LDP<S,D,Q,W,X>pre instruction, respectively. For each pair, there is a MIR test that verifies this optimization. Differential Revision: https://reviews.llvm.org/D99272 Change-Id: Ie97a20c8c716c08492fe229c22e14e3c98ef08b7
2021-04-30 17:19:48 +02:00
RET undef $lr, implicit $x0
...
---
name: 13-strqpre-sturqi-merge
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
- { reg: '$q0' }
- { reg: '$q1' }
frameInfo:
maxAlignment: 1
maxCallFrameSize: 0
machineFunctionInfo:
hasRedZone: false
body: |
bb.0.entry:
liveins: $q0, $q1, $x0
; CHECK-LABEL: name: 13-strqpre-sturqi-merge
; CHECK: liveins: $q0, $q1, $x0
CodeGen: Print/parse LLTs in MachineMemOperands This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
2021-05-20 04:25:51 +02:00
; CHECK: early-clobber $x0 = STPQpre renamable $q0, renamable $q1, renamable $x0, 3 :: (store (s128))
[AArch64] Adds a pre-indexed paired Load/Store optimization for LDR-STR. This patch merges STR<S,D,Q,W,X>pre-STR<S,D,Q,W,X>ui and LDR<S,D,Q,W,X>pre-LDR<S,D,Q,W,X>ui instruction pairs into a single STP<S,D,Q,W,X>pre and LDP<S,D,Q,W,X>pre instruction, respectively. For each pair, there is a MIR test that verifies this optimization. Differential Revision: https://reviews.llvm.org/D99272 Change-Id: Ie97a20c8c716c08492fe229c22e14e3c98ef08b7
2021-04-30 17:19:48 +02:00
; CHECK: RET undef $lr, implicit $x0
CodeGen: Print/parse LLTs in MachineMemOperands This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
2021-05-20 04:25:51 +02:00
early-clobber renamable $x0 = STRQpre killed renamable $q0, killed renamable $x0, 48 :: (store (s128))
STURQi killed renamable $q1, renamable $x0, 16 :: (store (s128))
[AArch64] Adds a pre-indexed paired Load/Store optimization for LDR-STR. This patch merges STR<S,D,Q,W,X>pre-STR<S,D,Q,W,X>ui and LDR<S,D,Q,W,X>pre-LDR<S,D,Q,W,X>ui instruction pairs into a single STP<S,D,Q,W,X>pre and LDP<S,D,Q,W,X>pre instruction, respectively. For each pair, there is a MIR test that verifies this optimization. Differential Revision: https://reviews.llvm.org/D99272 Change-Id: Ie97a20c8c716c08492fe229c22e14e3c98ef08b7
2021-04-30 17:19:48 +02:00
RET undef $lr, implicit $x0
...
---
name: 14-strqpre-sturqi-no-merge
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
- { reg: '$q0' }
- { reg: '$q1' }
frameInfo:
maxAlignment: 1
maxCallFrameSize: 0
machineFunctionInfo:
hasRedZone: false
body: |
bb.0.entry:
liveins: $q0, $q1, $x0
; CHECK-LABEL: name: 14-strqpre-sturqi-no-merge
; CHECK: liveins: $q0, $q1, $x0
CodeGen: Print/parse LLTs in MachineMemOperands This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
2021-05-20 04:25:51 +02:00
; CHECK: early-clobber renamable $x0 = STRQpre renamable $q0, renamable $x0, 48, implicit $w0 :: (store (s128))
; CHECK: STURQi renamable $q1, renamable $x0, 1 :: (store (s128))
[AArch64] Adds a pre-indexed paired Load/Store optimization for LDR-STR. This patch merges STR<S,D,Q,W,X>pre-STR<S,D,Q,W,X>ui and LDR<S,D,Q,W,X>pre-LDR<S,D,Q,W,X>ui instruction pairs into a single STP<S,D,Q,W,X>pre and LDP<S,D,Q,W,X>pre instruction, respectively. For each pair, there is a MIR test that verifies this optimization. Differential Revision: https://reviews.llvm.org/D99272 Change-Id: Ie97a20c8c716c08492fe229c22e14e3c98ef08b7
2021-04-30 17:19:48 +02:00
; CHECK: RET undef $lr, implicit $x0
CodeGen: Print/parse LLTs in MachineMemOperands This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
2021-05-20 04:25:51 +02:00
early-clobber renamable $x0 = STRQpre killed renamable $q0, killed renamable $x0, 48 :: (store (s128))
STURQi killed renamable $q1, renamable $x0, 1 :: (store (s128))
[AArch64] Adds a pre-indexed paired Load/Store optimization for LDR-STR. This patch merges STR<S,D,Q,W,X>pre-STR<S,D,Q,W,X>ui and LDR<S,D,Q,W,X>pre-LDR<S,D,Q,W,X>ui instruction pairs into a single STP<S,D,Q,W,X>pre and LDP<S,D,Q,W,X>pre instruction, respectively. For each pair, there is a MIR test that verifies this optimization. Differential Revision: https://reviews.llvm.org/D99272 Change-Id: Ie97a20c8c716c08492fe229c22e14e3c98ef08b7
2021-04-30 17:19:48 +02:00
RET undef $lr, implicit $x0
...
---
name: 15-strspre-strsui-unaligned-no-merge
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
- { reg: '$s0' }
- { reg: '$s1' }
frameInfo:
maxAlignment: 1
maxCallFrameSize: 0
machineFunctionInfo:
hasRedZone: false
body: |
bb.0.entry:
liveins: $s0, $s1, $x0
; CHECK-LABEL: name: 15-strspre-strsui-unaligned-no-merge
; CHECK: liveins: $s0, $s1, $x0
CodeGen: Print/parse LLTs in MachineMemOperands This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
2021-05-20 04:25:51 +02:00
; CHECK: early-clobber renamable $x0 = STRSpre renamable $s0, renamable $x0, 251, implicit $w0 :: (store (s32))
; CHECK: STRSui renamable $s1, renamable $x0, 1 :: (store (s32))
[AArch64] Adds a pre-indexed paired Load/Store optimization for LDR-STR. This patch merges STR<S,D,Q,W,X>pre-STR<S,D,Q,W,X>ui and LDR<S,D,Q,W,X>pre-LDR<S,D,Q,W,X>ui instruction pairs into a single STP<S,D,Q,W,X>pre and LDP<S,D,Q,W,X>pre instruction, respectively. For each pair, there is a MIR test that verifies this optimization. Differential Revision: https://reviews.llvm.org/D99272 Change-Id: Ie97a20c8c716c08492fe229c22e14e3c98ef08b7
2021-04-30 17:19:48 +02:00
; CHECK: RET undef $lr, implicit $x0
CodeGen: Print/parse LLTs in MachineMemOperands This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
2021-05-20 04:25:51 +02:00
early-clobber renamable $x0 = STRSpre killed renamable $s0, killed renamable $x0, 251 :: (store (s32))
STRSui killed renamable $s1, renamable $x0, 1 :: (store (s32))
[AArch64] Adds a pre-indexed paired Load/Store optimization for LDR-STR. This patch merges STR<S,D,Q,W,X>pre-STR<S,D,Q,W,X>ui and LDR<S,D,Q,W,X>pre-LDR<S,D,Q,W,X>ui instruction pairs into a single STP<S,D,Q,W,X>pre and LDP<S,D,Q,W,X>pre instruction, respectively. For each pair, there is a MIR test that verifies this optimization. Differential Revision: https://reviews.llvm.org/D99272 Change-Id: Ie97a20c8c716c08492fe229c22e14e3c98ef08b7
2021-04-30 17:19:48 +02:00
RET undef $lr, implicit $x0
...
[AArch64] Fix for the pre-indexed paired load/store optimization. This patch fixes an issue where a pre-indexed store e.g., STR x1, [x0, #24]! with a store like STR x0, [x0, #8] are merged into a single store: STP x1, x0, [x0, #24]! . They shouldn’t be merged because the second store uses x0 as both the stored value and the address and so it needs to be using the updated x0. Therefore, it should not be folded into a STP <>pre. Additionally a new test case is added to verify this fix. Differential Revision: https://reviews.llvm.org/D101888 Change-Id: I26f1985ac84e970961e2cdca23c590fa6773851a
2021-05-05 12:02:33 +02:00
---
name: 16-strxpre-strxui-same-reg-no-merge
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
- { reg: '$x1' }
- { reg: '$x2' }
frameInfo:
maxAlignment: 1
maxCallFrameSize: 0
machineFunctionInfo:
hasRedZone: false
body: |
bb.0.entry:
liveins: $x0, $x1, $x2
; CHECK-LABEL: name: 16-strxpre-strxui-same-reg-no-merge
; CHECK: liveins: $x0, $x1, $x2
CodeGen: Print/parse LLTs in MachineMemOperands This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
2021-05-20 04:25:51 +02:00
; CHECK: early-clobber renamable $x0 = STRXpre renamable $x1, renamable $x0, 24, implicit $w0 :: (store (s64))
; CHECK: STRXui renamable $x0, renamable $x0, 1 :: (store (s64))
[AArch64] Fix for the pre-indexed paired load/store optimization. This patch fixes an issue where a pre-indexed store e.g., STR x1, [x0, #24]! with a store like STR x0, [x0, #8] are merged into a single store: STP x1, x0, [x0, #24]! . They shouldn’t be merged because the second store uses x0 as both the stored value and the address and so it needs to be using the updated x0. Therefore, it should not be folded into a STP <>pre. Additionally a new test case is added to verify this fix. Differential Revision: https://reviews.llvm.org/D101888 Change-Id: I26f1985ac84e970961e2cdca23c590fa6773851a
2021-05-05 12:02:33 +02:00
; CHECK: RET undef $lr, implicit $x0
CodeGen: Print/parse LLTs in MachineMemOperands This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
2021-05-20 04:25:51 +02:00
early-clobber renamable $x0 = STRXpre killed renamable $x1, killed renamable $x0, 24 :: (store (s64))
STRXui renamable $x0, renamable $x0, 1 :: (store (s64))
[AArch64] Fix for the pre-indexed paired load/store optimization. This patch fixes an issue where a pre-indexed store e.g., STR x1, [x0, #24]! with a store like STR x0, [x0, #8] are merged into a single store: STP x1, x0, [x0, #24]! . They shouldn’t be merged because the second store uses x0 as both the stored value and the address and so it needs to be using the updated x0. Therefore, it should not be folded into a STP <>pre. Additionally a new test case is added to verify this fix. Differential Revision: https://reviews.llvm.org/D101888 Change-Id: I26f1985ac84e970961e2cdca23c590fa6773851a
2021-05-05 12:02:33 +02:00
RET undef $lr, implicit $x0
...
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