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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-25 12:12:47 +01:00
llvm-mirror/test/CodeGen/AArch64
Djordje Todorovic c793732c01 [RemoveRedundantDebugValues] Add a Pass that removes redundant DBG_VALUEs
This new MIR pass removes redundant DBG_VALUEs.

After the register allocator is done, more precisely, after
the Virtual Register Rewriter, we end up having duplicated
DBG_VALUEs, since some virtual registers are being rewritten
into the same physical register as some of existing DBG_VALUEs.
Each DBG_VALUE should indicate (at least before the LiveDebugValues)
variables assignment, but it is being clobbered for function
parameters during the SelectionDAG since it generates new DBG_VALUEs
after COPY instructions, even though the parameter has no assignment.
For example, if we had a DBG_VALUE $regX as an entry debug value
representing the parameter, and a COPY and after the COPY,
DBG_VALUE $virt_reg, and after the virtregrewrite the $virt_reg gets
rewritten into $regX, we'd end up having redundant DBG_VALUE.

This breaks the definition of the DBG_VALUE since some analysis passes
might be built on top of that premise..., and this patch tries to fix
the MIR with the respect to that.

This first patch performs bacward scan, by trying to detect a sequence of
consecutive DBG_VALUEs, and to remove all DBG_VALUEs describing one
variable but the last one:

For example:

(1) DBG_VALUE $edi, !"var1", ...
(2) DBG_VALUE $esi, !"var2", ...
(3) DBG_VALUE $edi, !"var1", ...
 ...

in this case, we can remove (1).

By combining the forward scan that will be introduced in the next patch
(from this stack), by inspecting the statistics, the RemoveRedundantDebugValues
removes 15032 instructions by using gdb-7.11 as a testbed.

Differential Revision: https://reviews.llvm.org/D105279
2021-07-14 04:29:42 -07:00
..
GlobalISel [AArch64][GlobalISel] Mark v2s64 -> v2p0 G_INTTOPTR as legal 2021-07-13 17:28:14 -07:00
2s-complement-asm.ll
128bit_load_store.ll
a57-csel.ll
aarch64_f16_be.ll
aarch64_tree_tests.ll
aarch64_win64cc_vararg.ll
aarch64-2014-08-11-MachineCombinerCrash.ll
aarch64-2014-12-02-combine-soften.ll
aarch64-a57-fp-load-balancing.ll
aarch64-address-type-promotion-assertion.ll
aarch64-address-type-promotion.ll
aarch64-addv.ll
aarch64-be-bv.ll
aarch64-bf16-dotprod-intrinsics.ll
aarch64-bf16-ldst-intrinsics.ll
aarch64-bif-gen.ll
aarch64-bit-gen.ll
aarch64-bswap-ext.ll
aarch64-codegen-prepare-atp.ll
aarch64-combine-fmul-fsub.mir
aarch64-DAGCombine-findBetterNeighborChains-crash.ll
aarch64-dup-ext-crash.ll
aarch64-dup-ext-scalable.ll
aarch64-dup-ext-vectortype-crash.ll
aarch64-dup-ext.ll
aarch64-dup-extract-scalable.ll
aarch64-dynamic-stack-layout.ll
aarch64-fix-cortex-a53-835769.ll
aarch64-fold-lslfast.ll
aarch64-gep-opt.ll
aarch64-insert-subvector-undef.ll
aarch64-interleaved-ld-combine.ll
aarch64-ldst-modified-baseReg.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
aarch64-ldst-no-premature-sp-pop.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
aarch64-ldst-subsuperReg-no-ldp.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
aarch64-load-ext.ll [AArch64] Add some more tests to CodeGen/AArch64/aarch64-load-ext.ll. NFC. 2021-07-01 15:15:21 +01:00
aarch64-loop-gep-opt.ll
aarch64-matmul.ll
aarch64-matrix-umull-smull.ll
aarch64-minmaxv.ll
aarch64-mov-debug-locs.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
aarch64-mull-masks.ll
aarch64-named-reg-w18.ll
aarch64-named-reg-x18.ll
aarch64-neon-v1i1-setcc.ll
aarch64-signedreturnaddress.ll [AArch64][v8.3A] Avoid inserting implicit landing pads (PACI*SP) 2021-06-24 18:24:32 +01:00
aarch64-smax-constantfold.ll
aarch64-smull.ll
aarch64-stp-cluster.ll
aarch64-sve-asm-negative.ll
aarch64-sve-asm.ll
aarch64-tail-dup-size.ll
aarch64-tbz.ll
aarch64-tryBitfieldInsertOpFromOr-crash.ll
aarch64-unroll-and-jam.ll [AArch64] Further enable UnrollAndJam 2021-06-04 14:18:49 +01:00
aarch64-vcvtfp2fxs-combine.ll
aarch64-vector-pcs.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
aarch64-vuzp.ll
aarch64-wide-shuffle.ll
aarch-multipart.ll
adc.ll
addcarry-crash.ll
addg_subg.mir
addr-of-ret-addr.ll
addsub_ext.ll
addsub-constant-folding.ll
addsub-shifted.ll
addsub.ll [SimplifyCFG] Tail-merging all blocks with ret terminator 2021-06-24 13:15:39 +03:00
align-down.ll
alloca.ll
analyze-branch.ll
analyzecmp.ll
and-mask-removal.ll
and-sink.ll
andandshift.ll
apple-latest-cpu.ll
argument-blocks-array-of-struct.ll [llvm][AArch64] Handle arrays of struct properly (from IR) 2021-06-16 13:56:01 +00:00
argument-blocks.ll
arm64_32-addrs.ll
arm64_32-atomics.ll
arm64_32-fastisel.ll
arm64_32-frame-pointers.ll
arm64_32-gep-sink.ll
arm64_32-memcpy.ll
arm64_32-neon.ll
arm64_32-null.ll
arm64_32-pointer-extend.ll
arm64_32-stack-pointers.ll
arm64_32-tls.ll
arm64_32-va.ll
arm64_32.ll
arm64-2011-03-09-CPSRSpill.ll
arm64-2011-03-17-AsmPrinterCrash.ll
arm64-2011-03-21-Unaligned-Frame-Index.ll
arm64-2011-04-21-CPSRBug.ll
arm64-2011-10-18-LdStOptBug.ll
arm64-2012-01-11-ComparisonDAGCrash.ll
arm64-2012-05-07-DAGCombineVectorExtract.ll
arm64-2012-05-07-MemcpyAlignBug.ll
arm64-2012-05-09-LOADgot-bug.ll
arm64-2012-05-22-LdStOptBug.ll
arm64-2012-06-06-FPToUI.ll
arm64-2012-07-11-InstrEmitterBug.ll
arm64-2013-01-13-ffast-fcmp.ll
arm64-2013-01-23-frem-crash.ll
arm64-2013-01-23-sext-crash.ll
arm64-2013-02-12-shufv8i8.ll
arm64-aapcs-be.ll
arm64-aapcs.ll
arm64-abi_align.ll
arm64-abi-hfa-args.ll
arm64-abi-varargs.ll
arm64-abi.ll
arm64-addp.ll
arm64-addr-mode-folding.ll
arm64-addr-type-promotion.ll
arm64-addrmode.ll
arm64-AdvSIMD-Scalar.ll
arm64-alloc-no-stack-realign.ll
arm64-alloca-frame-pointer-offset.ll
arm64-andCmpBrToTBZ.ll
arm64-ands-bad-peephole.ll
arm64-AnInfiniteLoopInDAGCombine.ll
arm64-anyregcc-crash.ll
arm64-anyregcc.ll
arm64-arith-saturating.ll
arm64-arith.ll
arm64-arm64-dead-def-elimination-flag.ll
arm64-assert-zext-sext.ll
arm64-atomic-128.ll
arm64-atomic.ll
arm64-bcc.ll
arm64-big-endian-bitconverts.ll
arm64-big-endian-eh.ll
arm64-big-endian-varargs.ll
arm64-big-endian-vector-callee.ll
arm64-big-endian-vector-caller.ll
arm64-big-imm-offsets.ll
arm64-big-stack.ll
arm64-bitfield-extract.ll
arm64-blockaddress.ll
arm64-build-vector.ll
arm64-builtins-linux.ll
arm64-call-tailcalls.ll
arm64-cast-opt.ll
arm64-ccmp-heuristics.ll
arm64-ccmp.ll
arm64-clrsb.ll
arm64-coalesce-ext.ll
arm64-coalescing-MOVi32imm.ll
arm64-code-model-large-darwin.ll
arm64-codegen-prepare-extload.ll
arm64-collect-loh-garbage-crash.ll
arm64-collect-loh-str.ll
arm64-collect-loh.ll
arm64-complex-ret.ll
arm64-const-addr.ll
arm64-constrained-fcmp-no-nans-opt.ll
arm64-convert-v4f64.ll
arm64-copy-tuple.ll
arm64-crc32.ll
arm64-crypto.ll
arm64-cse.ll
arm64-csel.ll
arm64-csldst-mmo.ll
arm64-custom-call-saved-reg.ll
arm64-cvt.ll
arm64-dagcombiner-convergence.ll
arm64-dagcombiner-dead-indexed-load.ll
arm64-dagcombiner-load-slicing.ll
arm64-darwin-cc.ll
arm64-dead-def-frame-index.ll
arm64-dead-register-def-bug.ll
arm64-detect-vec-redux.ll
arm64-dup.ll
arm64-early-ifcvt.ll
arm64-elf-calls.ll
arm64-elf-constpool.ll
arm64-EXT-undef-mask.ll
arm64-ext.ll
arm64-extend-int-to-fp.ll
arm64-extend.ll
arm64-extload-knownzero.ll
arm64-extract_subvector.ll
arm64-extract.ll
arm64-fast-isel-addr-offset.ll
arm64-fast-isel-alloca.ll
arm64-fast-isel-br.ll
arm64-fast-isel-call.ll
arm64-fast-isel-conversion-fallback.ll
arm64-fast-isel-conversion.ll
arm64-fast-isel-fcmp.ll
arm64-fast-isel-gv.ll
arm64-fast-isel-icmp.ll
arm64-fast-isel-indirectbr.ll
arm64-fast-isel-intrinsic.ll
arm64-fast-isel-materialize.ll
arm64-fast-isel-noconvert.ll
arm64-fast-isel-rem.ll
arm64-fast-isel-ret.ll
arm64-fast-isel-store.ll
arm64-fast-isel.ll
arm64-fastcc-tailcall.ll
arm64-fastisel-gep-promote-before-add.ll
arm64-fcmp-opt.ll
arm64-fcopysign.ll
arm64-fixed-point-scalar-cvt-dagcombine.ll
arm64-fma-combine-with-fpfusion.ll
arm64-fma-combines.ll
arm64-fmadd.ll
arm64-fmax-safe.ll
arm64-fmax.ll
arm64-fminv.ll
arm64-fml-combines.ll
arm64-fmuladd.ll
arm64-fold-address.ll
arm64-fold-lsl.ll
arm64-fp128-folding.ll
arm64-fp128.ll
arm64-fp-contract-zero.ll
arm64-fp-imm-size.ll
arm64-fp-imm.ll
arm64-fp.ll
arm64-fpcr.ll
arm64-frame-index.ll
arm64-global-address.ll
arm64-hello.ll
arm64-homogeneous-prolog-epilog-bad-outline.mir
arm64-homogeneous-prolog-epilog-frame-tail.ll
arm64-homogeneous-prolog-epilog-no-helper.ll
arm64-homogeneous-prolog-epilog.ll
arm64-i16-subreg-extract.ll
arm64-icmp-opt.ll
arm64-indexed-memory.ll
arm64-indexed-vector-ldst-2.ll
arm64-indexed-vector-ldst.ll [DAGCombine] Poison-prove scalarizeExtractedVectorLoad. 2021-05-30 11:40:55 +01:00
arm64-inline-asm-error-I.ll
arm64-inline-asm-error-J.ll
arm64-inline-asm-error-K.ll
arm64-inline-asm-error-L.ll
arm64-inline-asm-error-M.ll
arm64-inline-asm-error-N.ll
arm64-inline-asm-zero-reg-error.ll
arm64-inline-asm.ll
arm64-instruction-mix-remarks.ll [SimplifyCFG] Tail-merging all blocks with ret terminator 2021-06-24 13:15:39 +03:00
arm64-isel-or.ll [AArch64ISelDAGToDAG] Fix ORRWrs/ORRXrs usefulbits calculation bug 2021-07-06 00:38:42 +08:00
arm64-join-reserved.ll
arm64-jumptable.ll
arm64-large-frame.ll
arm64-ld1.ll
arm64-ld-from-st.ll
arm64-ldp-aa.ll
arm64-ldp-cluster.ll
arm64-ldp.ll
arm64-ldst-unscaled-pre-post.mir
arm64-ldur.ll
arm64-ldxr-stxr.ll
arm64-leaf.ll
arm64-long-shift.ll
arm64-memcpy-inline.ll
arm64-memset-inline.ll
arm64-memset-to-bzero-pgso.ll
arm64-memset-to-bzero.ll
arm64-misaligned-memcpy-inline.ll
arm64-misched-basic-A53.ll
arm64-misched-basic-A57.ll
arm64-misched-forwarding-A53.ll
arm64-misched-memdep-bug.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
arm64-misched-multimmo.ll
arm64-movi.ll
arm64-mte.ll
arm64-mul.ll
arm64-named-reg-alloc.ll
arm64-named-reg-notareg.ll
arm64-narrow-st-merge.ll
arm64-neg.ll
arm64-neon-2velem-high.ll
arm64-neon-2velem.ll
arm64-neon-3vdiff.ll
arm64-neon-aba-abd.ll
arm64-neon-across.ll
arm64-neon-add-pairwise.ll
arm64-neon-add-sub.ll
arm64-neon-copy.ll
arm64-neon-copyPhysReg-tuple.ll
arm64-neon-mul-div-cte.ll
arm64-neon-mul-div.ll
arm64-neon-scalar-by-elem-mul.ll
arm64-neon-select_cc.ll
arm64-neon-simd-ldst-one.ll
arm64-neon-simd-shift.ll
arm64-neon-simd-vget.ll
arm64-neon-v1i1-setcc.ll
arm64-neon-v8.1a.ll
arm64-neon-vector-list-spill.ll
arm64-neon-vector-shuffle-extract.ll
arm64-nvcast.ll
arm64-opt-remarks-lazy-bfi.ll
arm64-patchpoint-scratch-regs.ll
arm64-patchpoint-webkit_jscc.ll
arm64-patchpoint.ll
arm64-pic-local-symbol.ll
arm64-platform-reg.ll
arm64-popcnt.ll
arm64-prefetch.ll
arm64-preserve-most.ll
arm64-promote-const-complex-initializers.ll
arm64-promote-const.ll
arm64-redzone.ll
arm64-reg-copy-noneon.ll
arm64-register-offset-addressing.ll
arm64-register-pairing.ll
arm64-regress-f128csel-flags.ll
arm64-regress-interphase-shift.ll
arm64-regress-opt-cmp.mir
arm64-reserve-call-saved-reg.ll
arm64-reserved-arg-reg-call-error.ll
arm64-return-vector.ll
arm64-returnaddr.ll
arm64-rev.ll [Tests] Fix test broken by: 43c7ca8e4963 [AArch64][GlobalISel] Legalize store <2 x i16> 2021-07-13 11:36:36 -07:00
arm64-rounding.ll
arm64-scaled_iv.ll
arm64-scvt.ll
arm64-setcc-int-to-fp-combine.ll
arm64-shifted-sext.ll
arm64-shrink-v1i64.ll
arm64-shrink-wrapping.ll
arm64-simd-scalar-to-vector.ll
arm64-simplest-elf.ll
arm64-sincos.ll
arm64-sitofp-combine-chains.ll
arm64-sli-sri-opt.ll
arm64-smaxv.ll
arm64-sminv.ll
arm64-spill-lr.ll
arm64-spill-remarks-treshold-hotness.ll
arm64-spill-remarks.ll
arm64-spill.ll
arm64-sqshl-uqshl-i64Contant.ll
arm64-st1.ll
arm64-stack-no-frame.ll
arm64-stackmap-nops.ll
arm64-stackmap.ll
arm64-stackpointer.ll
arm64-stacksave.ll
arm64-storebytesmerge.ll
arm64-stp-aa.ll
arm64-stp.ll
arm64-strict-align.ll
arm64-stur.ll
arm64-subsections.ll
arm64-subvector-extend.ll
arm64-summary-remarks.ll
arm64-swizzle-tbl-i16-layout.ll
arm64-tbl.ll
arm64-this-return.ll
arm64-tls-darwin.ll
arm64-tls-dynamic-together.ll
arm64-tls-dynamics.ll
arm64-tls-initial-exec.ll
arm64-tls-local-exec.ll
arm64-trap.ll
arm64-triv-disjoint-mem-access.ll
arm64-trn.ll
arm64-trunc-store.ll
arm64-umaxv.ll
arm64-uminv.ll
arm64-umov.ll
arm64-unaligned_ldst.ll
arm64-uzp.ll
arm64-vaargs.ll
arm64-vabs.ll [AArch64] Add TableGen patterns to generate uaddlv 2021-06-18 17:23:26 +01:00
arm64-vadd.ll
arm64-vaddlv.ll
arm64-vaddv.ll
arm64-variadic-aapcs.ll
arm64-vbitwise.ll
arm64-vclz.ll
arm64-vcmp.ll
arm64-vcnt.ll
arm64-vcombine.ll
arm64-vcvt_f32_su32.ll
arm64-vcvt_f.ll
arm64-vcvt_n.ll
arm64-vcvt_su32_f32.ll
arm64-vcvt.ll
arm64-vcvtxd_f32_f64.ll
arm64-vecCmpBr.ll
arm64-vecFold.ll
arm64-vector-ext.ll
arm64-vector-imm.ll
arm64-vector-insertion.ll
arm64-vector-ldst.ll
arm64-vext_reverse.ll
arm64-vext.ll
arm64-vfloatintrinsics.ll Update @llvm.powi to handle different int sizes for the exponent 2021-06-17 09:38:28 +02:00
arm64-vhadd.ll
arm64-vhsub.ll
arm64-virtual_base.ll
arm64-vmax.ll
arm64-vminmaxnm.ll
arm64-vmovn.ll
arm64-vmul.ll
arm64-volatile.ll
arm64-vpopcnt.ll
arm64-vqadd.ll
arm64-vqsub.ll
arm64-vselect.ll
arm64-vsetcc_fp.ll
arm64-vshift.ll Recommit "[AArch64] Custom lower <4 x i8> loads" 2021-06-30 09:18:06 +01:00
arm64-vshr.ll
arm64-vshuffle.ll
arm64-vsqrt.ll
arm64-vsra.ll
arm64-vsub.ll
arm64-weak-reference.ll
arm64-windows-calls.ll
arm64-windows-tailcall.ll
arm64-xaluo.ll [AArch64] Optimize overflow checks for [s|u]mul.with.overflow.i32. 2021-07-12 15:30:42 -07:00
arm64-zero-cycle-regmov.ll
arm64-zero-cycle-zeroing.ll
arm64-zeroreg.ll
arm64-zext.ll
arm64-zextload-unscaled.ll
arm64-zip.ll
asm-large-immediate.ll
asm-print-comments.ll
asm-srcloc.ll
assertion-rc-mismatch.ll
atomic-ops-lse.ll [AArch64][RISCV] Make sure isel correctly honors failure orderings. 2021-05-28 12:47:40 -07:00
atomic-ops-not-barriers.ll
atomic-ops.ll
atomicrmw-O0.ll
atomicrmw-xchg-fp.ll [AtomicExpandPass][AArch64] Promote xchg with floating-point types to integer ones 2021-05-29 08:57:27 +02:00
autoupgrade-aarch64-neon-addp-float.ll
basic-pic.ll
bcmp-inline-small.ll
bf16-convert-intrinsics.ll
bf16-vector-bitcast.ll
bf16-vector-shuffle.ll
bf16.ll
bics.ll
big-callframe.ll
bisect-post-ra-machine-sink.mir
bitcast-promote-widen.ll
bitcast-v2i8.ll
bitcast.ll
bitfield-extract.ll
bitfield-insert-0.ll
bitfield-insert.ll [AArch64] Add regression test for missed bfi optimization. 2021-06-02 17:38:51 -07:00
bitfield.ll
bitreverse.ll [AArch64] Optimise bitreverse lowering in ISel 2021-06-02 12:51:12 +01:00
blockaddress.ll
bool-ext-inc.ll
bool-loads.ll
br-cond-not-merge.ll
br-to-eh-lpad.ll
br-undef-cond.ll
branch-folder-merge-mmos.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
branch-folder-oneinst.mir
branch-relax-alignment.ll Revert "Revert "Temporarily do not drop volatile stores before unreachable"" 2021-07-09 11:44:34 -04:00
branch-relax-asm.ll [SimplifyCFG] Tail-merging all blocks with ret terminator 2021-06-24 13:15:39 +03:00
branch-relax-bcc.ll Revert "Revert "Temporarily do not drop volatile stores before unreachable"" 2021-07-09 11:44:34 -04:00
branch-relax-block-size.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
branch-relax-cbz.ll [SimplifyCFG] Tail-merging all blocks with ret terminator 2021-06-24 13:15:39 +03:00
branch-target-enforcement-indirect-calls.ll
branch-target-enforcement.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
breg.ll
bswap-known-bits.ll
bti-branch-relaxation.ll
build-one-lane.ll
build-pair-isel.ll
build-vector-extract.ll
byval-type.ll
call-rv-marker.ll
callbr-asm-label.ll
callbr-asm-obj-file.ll
callee-save.ll
ccmp-successor-probs.mir
cfguard-checks.ll [SimplifyCFG] Tail-merging all blocks with ret terminator 2021-06-24 13:15:39 +03:00
cfguard-module-flag.ll
cfi_restore.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
cfinv-def-nzcv.mir
cfinv-use-nzcv.mir
cgp-trivial-phi-node.ll
cgp-usubo.ll [SimplifyCFG] Tail-merging all blocks with ret terminator 2021-06-24 13:15:39 +03:00
check-sign-bit-before-extension.ll [SimplifyCFG] Tail-merging all blocks with ret terminator 2021-06-24 13:15:39 +03:00
chkstk.ll
clang-section-macho.ll
cls.ll
cluster-frame-index.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
cmp-bool.ll
cmp-const-max.ll
cmp-frameindex.ll
cmp-select-sign.ll
cmp-to-cmn.ll
cmpwithshort.ll
cmpxchg-idioms.ll
cmpxchg-lse-even-regs.ll
cmpxchg-O0.ll
code-model-large-abs.ll
code-model-tiny-abs.ll
combine-and-like.ll
combine-comparisons-by-cse.ll [SimplifyCFG] Tail-merging all blocks with ret terminator 2021-06-24 13:15:39 +03:00
compare-branch.ll
compiler-ident.ll
complex-copy-noneon.ll
complex-fp-to-int.ll
complex-int-to-fp.ll
concat_vector-scalar-combine.ll
concat_vector-truncate-combine.ll
concat_vector-truncated-scalar-combine.ll
cond-br-tuning.ll [SimplifyCFG] Tail-merging all blocks with ret terminator 2021-06-24 13:15:39 +03:00
cond-sel-value-prop.ll
cond-sel.ll
const-shift-of-constmasked.ll
consthoist-gep.ll Revert "[AArch64LoadStoreOptimizer] Recommit: Generate more STPs by renaming registers earlier" 2021-06-23 09:54:16 +03:00
convertphitype.ll
copyprop.mir
cpus.ll
csel-zero-float.ll
csinc-cmp-removal.mir
csr-split.ll
ctpop-nonean.ll
cvt-fp-int-fp.ll
cxx-tlscc.ll
dag-combine-insert-subvector.ll
dag-combine-invaraints.ll
dag-combine-lifetime-end-store-typesize.ll
dag-combine-mul-shl.ll
dag-combine-select.ll
dag-combine-trunc-build-vec.ll
dag-numsignbits.ll
DAGCombine_vscale.ll
dbg-declare-tag-offset.ll
dbg-value-tag-offset.ll
debug-info-sve-dbg-declare.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
debug-info-sve-dbg-value.mir
debugtrap.ll
directcond.ll
div_minsize.ll
div-rem-pair-recomposition-signed.ll
div-rem-pair-recomposition-unsigned.ll
divrem.ll
dllexport.ll
dllimport.ll
dont-shrink-wrap-stack-mayloadorstore.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
dont-take-over-the-world.ll
dp1.ll
dp2.ll
dp-3source.ll
dwarf-cfi.ll
early-ifcvt-regclass-mismatch.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
early-ifcvt-same-value.mir
eh_recoverfp.ll
ehcontguard.ll
elf-globals-pic.ll
elf-globals-static.ll
elf-preemption.ll
elim-dead-mi.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
eliminate-trunc.ll
emutls_generic.ll
emutls.ll
eon.ll
expand-blr-rvmarker-pseudo.mir
expand-movi-renamable.mir
expand-select.ll
expand-vector-rot.ll
ext-narrow-index.ll
extern-weak.ll
extra-callee-save.mir
extract-bits.ll
extract-insert.ll
extract-lowbits.ll
extract.ll
f16-convert.ll
f16-imm.ll
f16-instructions.ll [SimplifyCFG] Tail-merging all blocks with ret terminator 2021-06-24 13:15:39 +03:00
fabs.ll
fadd-combines.ll [DAGCombine] reassoc flag shouldn't enable contract 2021-06-21 21:15:43 +00:00
faddp-half.ll
faddp.ll
falkor-hwpf-fix.ll
falkor-hwpf-fix.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
falkor-hwpf.ll
fast-isel-address-extends.ll
fast-isel-addressing-modes.ll
fast-isel-assume.ll
fast-isel-atomic.ll
fast-isel-branch_weights.ll
fast-isel-branch-cond-mask.ll
fast-isel-branch-cond-split.ll [SimplifyCFG] Tail-merging all blocks with ret terminator 2021-06-24 13:15:39 +03:00
fast-isel-branch-uncond-debug.ll
fast-isel-call-return.ll
fast-isel-cbz.ll
fast-isel-cmp-branch.ll
fast-isel-cmp-vec.ll
fast-isel-cmpxchg.ll
fast-isel-dbg.ll
fast-isel-erase.ll
fast-isel-folded-shift.ll
fast-isel-folding.ll
fast-isel-fpimm.ll
fast-isel-gep.ll
fast-isel-int-ext2.ll
fast-isel-int-ext3.ll
fast-isel-int-ext4.ll
fast-isel-int-ext5.ll
fast-isel-int-ext.ll
fast-isel-intrinsic.ll
fast-isel-logic-op.ll
fast-isel-memcpy.ll
fast-isel-mul.ll
fast-isel-runtime-libcall.ll
fast-isel-sdiv.ll
fast-isel-select.ll
fast-isel-shift.ll
fast-isel-sp-adjust.ll
fast-isel-sqrt.ll
fast-isel-switch-phi.ll
fast-isel-tail-call.ll
fast-isel-tbz.ll
fast-isel-trunc.ll
fast-isel-vector-arithmetic.ll
fast-isel-vret.ll
fast-regalloc-empty-bb-with-liveins.mir
fastcc-reserved.ll
fastcc.ll
fastisel-debugvalue-undef.ll
fcmp.ll
fcopysign.ll
fcsel-zero.ll
fcvt_combine.ll
fcvt-fixed.ll
fcvt-int.ll
fdiv_combine.ll
fdiv-combine.ll
fence-singlethread.ll
fjcvtzs.ll
fjcvtzs.mir
flags-multiuse.ll
floatdp_1source.ll
floatdp_2source.ll
fmov-imm-licm.ll
fold-constants.ll
fold-global-offsets.ll
fp16_intrinsic_lane.ll
fp16_intrinsic_scalar_1op.ll
fp16_intrinsic_scalar_2op.ll
fp16_intrinsic_scalar_3op.ll
fp16_intrinsic_vector_1op.ll
fp16_intrinsic_vector_2op.ll
fp16_intrinsic_vector_3op.ll
fp16-fmla.ll
fp16-v4-instructions.ll
fp16-v8-instructions.ll
fp16-v16-instructions.ll
fp16-vector-bitcast.ll
fp16-vector-load-store.ll
fp16-vector-nvcast.ll
fp16-vector-shuffle.ll
fp128-folding.ll
fp-cond-sel.ll
fp-const-fold.ll
fp-dp3.ll
fp-intrinsics.ll
fpconv-vector-op-scalarize-strict.ll
fpconv-vector-op-scalarize.ll
fpenv.ll
fpimm.ll
fptosi-sat-scalar.ll
fptosi-sat-vector.ll
fptoui-sat-scalar.ll
fptoui-sat-vector.ll
fptouint-i8-zext.ll
frameaddr.ll
framelayout-fp-csr.ll
framelayout-frame-record.mir
framelayout-offset-immediate-change.mir
framelayout-scavengingslot.mir
framelayout-sve-basepointer.mir
framelayout-sve-calleesaves-fix.mir
framelayout-sve-scavengingslot.mir
framelayout-sve.mir
framelayout-unaligned-fp.ll
free-zext.ll
frintn.ll
ftrunc.ll
func-argpassing.ll
func-calls.ll
funclet-local-stack-size.ll
funclet-match-add-sub-stack.ll
funcptr_cast.ll
function-info-noredzone-present.ll
function-subtarget-features.ll
funnel-shift-rot.ll
funnel-shift.ll
gep-nullptr.ll
ghc-cc.ll
global-alignment.ll
global-merge-1.ll
global-merge-2.ll
global-merge-3.ll
global-merge-4.ll
global-merge-group-by-use.ll
global-merge-hidden-minsize.ll
global-merge-ignore-single-use-minsize.ll
global-merge-ignore-single-use.ll
global-merge-minsize.ll
global-merge.ll
got-abuse.ll
half.ll
hints.ll
hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
hoist-and-by-const-from-shl-in-eqcmp-zero.ll
hwasan-check-memaccess.ll
hwasan-prefer-fp.ll
i1-contents.ll
i128_volatile_load_store.ll
i128-align.ll
i128-fast-isel-fallback.ll
iabs.ll
ifcvt-select.ll
illegal-float-ops.ll Update @llvm.powi to handle different int sizes for the exponent 2021-06-17 09:38:28 +02:00
ilp32-tlsdesc.ll
ilp32-va.ll
immcost.ll
implicit-null-check.ll [SimplifyCFG] Tail-merging all blocks with ret terminator 2021-06-24 13:15:39 +03:00
implicit-sret.ll
inc-of-add.ll
init-array.ll
inline-asm-blockaddress.ll
inline-asm-clobber.ll
inline-asm-constraints-bad-sve.ll
inline-asm-constraints-badI.ll
inline-asm-constraints-badK2.ll
inline-asm-constraints-badK.ll
inline-asm-constraints-badL.ll
inline-asm-globaladdress.ll
inline-asm-i-constraint-i1.ll
inline-asm-multilevel-gep.ll
inlineasm-illegal-type.ll
inlineasm-ldr-pseudo.ll
inlineasm-output-template.ll
inlineasm-S-constraint.ll [SimplifyCFG] FoldTwoEntryPHINode(): don't fold if either block has it's address taken 2021-06-20 12:37:14 +03:00
inlineasm-X-allocation.ll
inlineasm-X-constraint.ll
insert-subvector-res-legalization.ll [SelectionDAG] Simplify PromoteIntRes_INSERT_SUBVECTOR to only handle result 2021-07-12 15:20:44 +00:00
intrinsics-memory-barrier.ll
irg_sp_tagp.ll
irg-nomem.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
irg.ll
isinf.ll
jti-correct-datatype.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
jump-table-32.ll
jump-table-compress.mir
jump-table-duplicate.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
jump-table-exynos.ll
jump-table.ll
known-never-nan.ll
lack-of-signed-truncation-check.ll
landingpad-ifcvt.ll
large_shift.ll
large-consts.ll
large-stack-cmp.ll
large-stack.ll
ldp-stp-scaled-unscaled-pairs.ll
ldradr.ll
ldrpre-ldr-merge.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
ldst-miflags.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
ldst-nopreidx-sp-redzone.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
ldst-opt-aa.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
ldst-opt-after-block-placement.ll [SimplifyCFG] Tail-merging all blocks with ret terminator 2021-06-24 13:15:39 +03:00
ldst-opt-mte-with-dbg.mir
ldst-opt-mte.mir
ldst-opt-non-imm-offset.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
ldst-opt-zr-clobber.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
ldst-opt.ll Revert "[AArch64LoadStoreOptimizer] Recommit: Generate more STPs by renaming registers earlier" 2021-06-23 09:54:16 +03:00
ldst-opt.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
ldst-paired-aliasing.ll [SimplifyCFG] Tail-merging all blocks with ret terminator 2021-06-24 13:15:39 +03:00
ldst-regoffset.ll
ldst-unscaledimm.ll
ldst-unsignedimm.ll
ldst-zero.ll
legalize-bug-bogus-cpu.ll
lit.local.cfg
literal_pools_float.ll
live-debugvalues-sve.mir [X86] Return src/dest register from stack spill/restore recogniser 2021-07-09 18:12:30 +01:00
live-interval-analysis.mir
llrint-conv-fp16.ll
llrint-conv.ll
llround-conv-fp16.ll
llround-conv.ll
llvm-ir-to-intrinsic.ll
llvm-masked-gather-legal-for-sve.ll
llvm-masked-scatter-legal-for-sve.ll
load-combine-big-endian.ll
load-combine.ll
load-store-forwarding.ll
local_vars.ll
logical_shifted_reg.ll [SimplifyCFG] Tail-merging all blocks with ret terminator 2021-06-24 13:15:39 +03:00
logical-imm.ll
loh-adrp-add-ldr-clobber.mir
loh-use-between-adrp-add.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
loh.mir
loop-micro-op-buffer-size-t99.ll [LoopUnroll] Simplify optimization remarks 2021-06-18 23:47:03 +02:00
loop-sink-limit.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
loop-sink.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
lower-ptrmask.ll
lower-range-metadata-func-call.ll
lowerMUL-newload.ll
lrint-conv-fp16-win.ll
lrint-conv-fp16.ll
lrint-conv-win.ll
lrint-conv.ll
lround-conv-fp16-win.ll
lround-conv-fp16.ll
lround-conv-win.ll
lround-conv.ll
ls64-intrinsics.ll
machine_cse_illegal_hoist.ll
machine_cse_impdef_killflags.ll
machine_cse.ll
machine-combiner-instr-fmf.mir
machine-combiner-madd.ll
machine-combiner.ll
machine-combiner.mir
machine-copy-prop.ll
machine-copy-remove.ll
machine-copy-remove.mir
machine-cp-clobbers.mir
machine-dead-copy.mir
machine-licm-sink-instr.ll
machine-outliner-2fixup-blr-terminator.mir
machine-outliner-all-stack.mir
machine-outliner-bad-adrp.mir
machine-outliner-bad-register.mir
machine-outliner-bti.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
machine-outliner-calls.mir
machine-outliner-cfi-tail-some.mir
machine-outliner-cfi-tail.mir
machine-outliner-cfi.mir
machine-outliner-compatible-candidates.mir
machine-outliner-default.mir
machine-outliner-drop-stack.mir
machine-outliner-flags.ll
machine-outliner-function-annotate.mir
machine-outliner-inline-asm-adrp.mir
machine-outliner-iterative-2.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
machine-outliner-iterative.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
machine-outliner-no-noreturn-no-stack.mir
machine-outliner-noredzone.ll
machine-outliner-noreturn-no-stack.mir
machine-outliner-noreturn-save-lr.mir
machine-outliner-ordering.mir
machine-outliner-outline-bti.ll
machine-outliner-regsave.mir
machine-outliner-remarks.ll
machine-outliner-retaddr-sign-cfi.ll
machine-outliner-retaddr-sign-diff-scope-same-key.ll
machine-outliner-retaddr-sign-non-leaf.ll
machine-outliner-retaddr-sign-regsave.mir
machine-outliner-retaddr-sign-same-scope-diff-key.ll
machine-outliner-retaddr-sign-same-scope-same-key-a.ll
machine-outliner-retaddr-sign-same-scope-same-key-b.ll
machine-outliner-retaddr-sign-sp-mod.ll [AArch64][v8.3A] Avoid inserting implicit landing pads (PACI*SP) 2021-06-24 18:24:32 +01:00
machine-outliner-retaddr-sign-sp-mod.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
machine-outliner-retaddr-sign-subtarget.ll [AArch64][v8.3A] Avoid inserting implicit landing pads (PACI*SP) 2021-06-24 18:24:32 +01:00
machine-outliner-retaddr-sign-thunk.ll
machine-outliner-retaddr-sign-v8-3.ll [AArch64][v8.3A] Avoid inserting implicit landing pads (PACI*SP) 2021-06-24 18:24:32 +01:00
machine-outliner-side-effect-2.mir
machine-outliner-side-effect.mir
machine-outliner-size-info.mir
machine-outliner-tail.ll
machine-outliner-throw2.ll
machine-outliner-throw.ll
machine-outliner-thunk.ll
machine-outliner-unsafe-stack-call.mir
machine-outliner.ll
machine-outliner.mir
machine-scheduler.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
machine-sink-getmemoperandwithoffset.mir
machine-sink-kill-flags.ll
machine-sink-zr.mir
machine-zero-copy-remove.mir
macho-global-symbols.ll
macho-trap.ll
macro-fusion-last.mir
macro-fusion.ll
madd-combiner.ll
madd-lohi.ll
mature-mc-support.ll
max-jump-table.ll
memcpy-f128.ll
memcpy-scoped-aa.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
memsize-remarks.ll [Remarks] Make memsize remarks report as an analysis, not a missed opportunity. 2021-06-22 18:22:47 -07:00
merge-store-dependency.ll
merge-store.ll
merge-trunc-store.ll
mergestores_noimplicitfloat.ll
midpoint-int.ll
min-jump-table.ll
min-max.ll [AArch64] Add test for min/max 2021-07-01 13:22:51 +01:00
mingw-refptr.ll
minmax-of-minmax.ll
minmax.ll
misched-fusion-addr.ll
misched-fusion-aes.ll
misched-fusion-arith-logic.mir
misched-fusion-crypto-eor.mir
misched-fusion-csel.ll
misched-fusion-lit.ll
misched-fusion.ll
misched-stp.ll
mla_mls_merge.ll
mlicm-stack-write-check.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
movimm-wzr.mir
movw-consts.ll
movw-shift-encoding.ll
mul_by_elt.ll
mul_pow2.ll
mul-lohi.ll
multi-vector-store-size.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
named-vector-shuffle-reverse-neon.ll
named-vector-shuffle-reverse-sve.ll
named-vector-shuffles-neon.ll
named-vector-shuffles-sve.ll
neg-abs.ll
neg-imm.ll
neon_rbit.ll [AArch64] Optimise bitreverse lowering in ISel 2021-06-02 12:51:12 +01:00
neon-bitcast.ll
neon-bitselect.ll
neon-bitwise-instructions.ll [AArch64] Add more tests related to vselect with constant condition. 2021-07-06 17:06:22 -07:00
neon-compare-instructions.ll
neon-diagnostics.ll
neon-dot-product.ll
neon-dotpattern.ll
neon-dotreduce.ll
neon-extract.ll
neon-fma-FMF.ll
neon-fma.ll
neon-fp16fml.ll
neon-fpextend_f16.ll
neon-fpround_f128.ll
neon-idiv.ll
neon-inline-asm-16-bit-fp.ll
neon-mla-mls.ll
neon-mov.ll
neon-or-combine.ll
neon-perm.ll
neon-reverseshuffle.patch
neon-sad.ll [AArch64] Add TableGen patterns to generate uaddlv 2021-06-18 17:23:26 +01:00
neon-scalar-by-elem-fma.ll
neon-scalar-copy.ll
neon-sha3.ll
neon-shift-left-long.ll
neon-shift-neg.ll [DAG] Fold neg(splat(neg(x)) -> splat(x) 2021-06-25 19:53:29 +01:00
neon-sm4-sm3.ll
neon-stepvector.ll
neon-truncstore.ll [AArch64] Added tests to neon-truncstore.ll. NFC. 2021-06-28 17:44:46 +01:00
neon-uaddlv.ll [AArch64] Add TableGen patterns to generate uaddlv 2021-06-18 17:23:26 +01:00
neon-vcadd.ll
neon-vcmla.ll
neon-vmull-high-p64.ll
neon-wide-splat.ll
nest-register.ll
no_cfi.ll
no-fp-asm-clobbers-crash.ll
no-quad-ldp-stp.ll
no-stack-arg-probe.ll
nomerge.ll
nonlazybind.ll
nontemporal.ll
note-gnu-property-pac-bti-0.ll
note-gnu-property-pac-bti-1.ll
note-gnu-property-pac-bti-2.ll
note-gnu-property-pac-bti-3.ll
note-gnu-property-pac-bti-4.ll
nzcv-save.ll
O0-pipeline.ll [RemoveRedundantDebugValues] Add a Pass that removes redundant DBG_VALUEs 2021-07-14 04:29:42 -07:00
O3-pipeline.ll [RemoveRedundantDebugValues] Add a Pass that removes redundant DBG_VALUEs 2021-07-14 04:29:42 -07:00
optimize-cond-branch.ll [SimplifyCFG] Tail-merging all blocks with ret terminator 2021-06-24 13:15:39 +03:00
optimize-imm.ll
or-combine.ll
overeager_mla_fusing.ll
overlapping-copy-bundle-cycle.mir
overlapping-copy-bundle.mir
pacbti-llvm-generated-funcs-1.ll
pacbti-llvm-generated-funcs-2.ll [AArch64][v8.3A] Avoid inserting implicit landing pads (PACI*SP) 2021-06-24 18:24:32 +01:00
pacbti-module-attrs.ll [AArch64][v8.3A] Avoid inserting implicit landing pads (PACI*SP) 2021-06-24 18:24:32 +01:00
paired-load.ll
parity.ll
partial-pipeline-execution.ll
patchable-function-entry-bti.ll
patchable-function-entry-empty.mir
patchable-function-entry.ll
PBQP-chain.ll
PBQP-coalesce-benefit.ll
PBQP-csr.ll
PBQP.ll
peephole-and-tst.ll
peephole-opt-check-cflags.mir
phi-dbg.ll
PHIElimination-crash.mir
PHIElimination-debugloc.mir
pic-eh-stubs.ll
pie.ll
popcount.ll
post-ra-machine-sink.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
postra-mi-sched.ll
pow.75.ll
pow.ll
powi-windows.ll Update @llvm.powi to handle different int sizes for the exponent 2021-06-17 09:38:28 +02:00
pr27816.ll
pr33172.ll [NFC][Codegen] Tune a few tests to not end with a naked unreachable terminator 2021-07-02 23:33:30 +03:00
pr40091.ll
pr48188.ll
pr49781.ll
preferred-alignment.ll
preferred-function-alignment.ll
prefixdata.ll
preserve_mostcc.ll
print-mrs-system-register.ll
prologue-epilogue-remarks.mir
pull-binop-through-shift.ll
pull-conditional-binop-through-shift.ll
qmovn.ll [AArch64] Add S/UQXTRN tablegen patterns. 2021-07-03 07:57:19 +01:00
ragreedy-csr.ll
ragreedy-local-interval-cost.ll
rand.ll
rbit.ll
read-pc.ll
readcyclecounter.ll
README
recp-fastmath.ll
reduce-and.ll [AArch64] Add CodeGen tests for vector reduction intrinsics. NFC 2021-06-23 13:46:16 +01:00
reduce-or.ll [AArch64] Add CodeGen tests for vector reduction intrinsics. NFC 2021-06-23 13:46:16 +01:00
reduce-xor.ll [AArch64] Add CodeGen tests for vector reduction intrinsics. NFC 2021-06-23 13:46:16 +01:00
redundant-copy-elim-empty-mbb.ll
Redundantstore.ll
reg-scavenge-frame.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
regcoal-physreg.mir
regress-bitcast-formals.ll
regress-combine-extract-vectors.ll
regress-f128csel-flags.ll
regress-fp128-livein.ll
regress-tail-livereg.ll
regress-tblgen-chains.ll
regress-w29-reserved-with-fp.ll
reloc-specifiers.mir
rem_crash.ll
remat-float0.ll
remat.ll
returnaddr.ll
reverse-csr-restore-seq.mir
rm_redundant_cmp.ll
rmif-def-nzcv.mir
rmif-use-nzcv.mir
rotate-extract.ll
rotate.ll
round-conv.ll
round-fptosi-sat-scalar.ll
round-fptoui-sat-scalar.ll
rvmarker-pseudo-expansion-and-outlining.mir
sadd_sat_plus.ll
sadd_sat_vec.ll Recommit "[AArch64] Custom lower <4 x i8> loads" 2021-06-30 09:18:06 +01:00
sadd_sat.ll
sat-add.ll
scalable-vector-promotion.ll
sched-past-vector-ldst.ll
scheduledag-constreg.mir
sdag-no-typesize-warnings-regandsizes.ll
sdag-store-merging-bug.ll
sdivpow2.ll
seh_funclet_x1.ll
seh-finally.ll
select_cc.ll
select_const.ll
select_fmf.ll
select-with-and-or.ll
selectcc-to-shiftand.ll
selectiondag-order.ll
semantic-interposition-asm.ll
seqpaircopy.mir
seqpairspill.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
setcc-takes-i32.ll
setcc-type-mismatch.ll
setf8-def-nzcv.mir
setf8-use-nzcv.mir
setf16-def-nzcv.mir
setf16-use-nzcv.mir
settag-merge-order.ll
settag-merge.ll
settag-merge.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
settag.ll
shadow-call-stack.ll
shift_minsize.ll
shift-amount-mod.ll
shift-by-signext.ll
shift-logic.ll
shift-mod.ll
shrink-constant-multiple-users.ll
shrink-wrap.ll
shrink-wrapping-vla.ll
shuffle-mask-legal.ll
sibling-call.ll
sign-return-address-cfi-negate-ra-state.ll [AArch64][v8.3A] Avoid inserting implicit landing pads (PACI*SP) 2021-06-24 18:24:32 +01:00
sign-return-address.ll [AArch64][v8.3A] Avoid inserting implicit landing pads (PACI*SP) 2021-06-24 18:24:32 +01:00
signbit-shift.ll
signed-truncation-check.ll
simple-macho.ll
sincos-expansion.ll
sincospow-vector-expansion.ll
sink-addsub-of-const.ll
sink-copy-for-shrink-wrap.ll
sitofp-fixed-legal.ll
space.ll
special-reg.ll
speculation-hardening-dagisel.ll
speculation-hardening-loads.ll
speculation-hardening-sls-blr.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
speculation-hardening-sls.ll
speculation-hardening-sls.mir
speculation-hardening.ll
speculation-hardening.mir
spill-fold.ll
spill-fold.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
spill-stack-realignment.mir
spill-undef.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
spillfill-sve.ll
spillfill-sve.mir
split-vector-insert.ll [TargetLowering][AArch64][SVE] Take into account accessed type when clamping address 2021-06-30 13:30:18 +01:00
sponentry.ll
sqrt-fastmath.ll
srem-lkk.ll
srem-seteq-illegal-types.ll
srem-seteq-optsize.ll
srem-seteq-vec-nonsplat.ll [AArch64] Remove AArch64ISD::NEG 2021-06-05 19:54:42 +01:00
srem-seteq-vec-splat.ll
srem-seteq.ll
srem-vector-lkk.ll
ssub_sat_plus.ll
ssub_sat_vec.ll Recommit "[AArch64] Custom lower <4 x i8> loads" 2021-06-30 09:18:06 +01:00
ssub_sat.ll
stack_guard_remat.ll
stack-guard-reassign.ll
stack-guard-reassign.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
stack-guard-remat-bitcast.ll
stack-guard-sysreg.ll
stack-guard-vaarg.ll
stack-id-pei-alloc.mir
stack-id-stackslot-scavenging.mir
stack-protector-musttail.ll
stack-protector-target.ll
stack-tagging-dbg.ll [DebugInfo] Correctly update dbg.values with duplicated location ops 2021-07-14 11:17:24 +01:00
stack-tagging-ex-1.ll
stack-tagging-ex-2.ll
stack-tagging-initializer-merge.ll
stack-tagging-unchecked-ld-st.ll
stack-tagging-untag-placement.ll
stack-tagging.ll
stackguard-internal.ll
stackmap-frame-setup.ll
stackmap-liveness.ll
stackmap.ll
statepoint-call-lowering.ll [SimplifyCFG] Tail-merging all blocks with ret terminator 2021-06-24 13:15:39 +03:00
stgp.ll
store_merge_pair_offset.ll
stp-opt-with-renaming-debug.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
stp-opt-with-renaming-ld3.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
stp-opt-with-renaming-reserved-regs.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
stp-opt-with-renaming.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
strict-fp-int-promote.ll
strpre-str-merge.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
strqro.ll
strqu.ll
sub1.ll
sub-of-bias.ll
sub-of-not.ll
sub-splat-sub.ll [DAG] Fold neg(splat(neg(x)) -> splat(x) 2021-06-25 19:53:29 +01:00
subs-to-sub-opt.ll
sve2-bitwise-ternary.ll
sve2-int-addsub-long.ll
sve2-int-mul.ll
sve2-int-mulh.ll
sve2-intrinsics-binary-narrowing-add-sub.ll
sve2-intrinsics-binary-narrowing-shr.ll
sve2-intrinsics-bit-permutation.ll
sve2-intrinsics-character-match.ll
sve2-intrinsics-complex-dot.ll
sve2-intrinsics-contiguous-conflict-detection.ll
sve2-intrinsics-crypto.ll
sve2-intrinsics-fp-converts.ll
sve2-intrinsics-fp-int-binary-logarithm.ll
sve2-intrinsics-fp-widening-mul-acc.ll
sve2-intrinsics-int-arith-imm.ll
sve2-intrinsics-int-mul-lane.ll
sve2-intrinsics-non-widening-pairwise-arith.ll
sve2-intrinsics-nt-gather-loads-32bit-unscaled-offset.ll
sve2-intrinsics-nt-gather-loads-64bit-scaled-offset.ll
sve2-intrinsics-nt-gather-loads-64bit-unscaled-offset.ll
sve2-intrinsics-nt-gather-loads-vector-base-scalar-offset.ll
sve2-intrinsics-nt-scatter-stores-32bit-unscaled-offset.ll
sve2-intrinsics-nt-scatter-stores-64bit-scaled-offset.ll
sve2-intrinsics-nt-scatter-stores-64bit-unscaled-offset.ll
sve2-intrinsics-nt-scatter-stores-vector-base-scalar-offset.ll
sve2-intrinsics-perm-tb.ll
sve2-intrinsics-polynomial-arithmetic-128.ll
sve2-intrinsics-polynomial-arithmetic.ll
sve2-intrinsics-unary-narrowing.ll
sve2-intrinsics-uniform-complex-arith.ll
sve2-intrinsics-uniform-dsp-zeroing.ll
sve2-intrinsics-uniform-dsp.ll [AArch64][SVE] Add support for using reverse forms of SVE2 shifts 2021-06-04 12:56:53 +01:00
sve2-intrinsics-vec-hist-count.ll
sve2-intrinsics-while.ll
sve2-intrinsics-widening-complex-int-arith.ll
sve2-intrinsics-widening-dsp.ll
sve2-intrinsics-widening-pairwise-arith.ll
sve2-mla-indexed.ll
sve2-mla-unpredicated.ll
sve-alloca-stackid.ll
sve-bad-intrinsics.ll
sve-bad-select.ll
sve-bit-counting-pred.ll
sve-bit-counting.ll
sve-bitcast.ll [AArch64] Optimize SVE bitcasts of unpacked types. 2021-07-01 15:35:48 -07:00
sve-breakdown-scalable-vectortype.ll [AArch64] Simplify sve-breakdown-scalable-vectortype.ll. 2021-07-07 12:32:17 -07:00
sve-callbyref-notailcall.ll
sve-calling-convention-byref.ll
sve-calling-convention-mixed.ll
sve-calling-convention-tuple-types.ll
sve-calling-convention.ll
sve-cmp-select.ll
sve-cntp-combine.ll
sve-coalesce-ptrue-intrinsics.ll
sve-copy-zprpair.mir
sve-expand-div.ll [SelectionDAG] Extend FoldConstantVectorArithmetic to SPLAT_VECTOR 2021-06-04 09:53:15 +01:00
sve-extract-element.ll
sve-extract-subvector.ll
sve-extract-vector.ll [TargetLowering][AArch64][SVE] Take into account accessed type when clamping address 2021-06-30 13:30:18 +01:00
sve-fcmp.ll [AArch64][SVE] Add ISel patterns for floating point compare with zero instructions 2021-07-08 10:46:12 +00:00
sve-fcvt.ll
sve-fix-length-and-combine-512.ll
sve-fixed-length-bit-counting.ll
sve-fixed-length-bitcast.ll
sve-fixed-length-bitselect.ll
sve-fixed-length-concat.ll
sve-fixed-length-extract-vector-elt.ll
sve-fixed-length-float-compares.ll
sve-fixed-length-fp-arith.ll
sve-fixed-length-fp-extend-trunc.ll
sve-fixed-length-fp-minmax.ll
sve-fixed-length-fp-reduce.ll
sve-fixed-length-fp-rounding.ll
sve-fixed-length-fp-select.ll
sve-fixed-length-fp-to-int.ll
sve-fixed-length-fp-vselect.ll
sve-fixed-length-insert-vector-elt.ll
sve-fixed-length-int-arith.ll
sve-fixed-length-int-compares.ll
sve-fixed-length-int-div.ll
sve-fixed-length-int-extends.ll
sve-fixed-length-int-immediates.ll
sve-fixed-length-int-log.ll
sve-fixed-length-int-minmax.ll
sve-fixed-length-int-mulh.ll
sve-fixed-length-int-reduce.ll
sve-fixed-length-int-rem.ll
sve-fixed-length-int-select.ll
sve-fixed-length-int-shifts.ll
sve-fixed-length-int-to-fp.ll
sve-fixed-length-int-vselect.ll
sve-fixed-length-loads.ll
sve-fixed-length-log-reduce.ll
sve-fixed-length-masked-gather.ll [llvm][sve] Lowering for VLS truncating stores 2021-07-12 11:14:17 +01:00
sve-fixed-length-masked-loads.ll [AArch64][SVE] DAG combine SETCC_MERGE_ZERO of a SETCC_MERGE_ZERO 2021-06-28 15:06:06 +01:00
sve-fixed-length-masked-scatter.ll [AArch64][SVE] Add ISel patterns for floating point compare with zero instructions 2021-07-08 10:46:12 +00:00
sve-fixed-length-masked-stores.ll [AArch64][SVE] DAG combine SETCC_MERGE_ZERO of a SETCC_MERGE_ZERO 2021-06-28 15:06:06 +01:00
sve-fixed-length-rev.ll
sve-fixed-length-shuffles.ll
sve-fixed-length-splat-vector.ll
sve-fixed-length-stores.ll
sve-fixed-length-subvector.ll
sve-fixed-length-trunc-stores.ll [llvm][sve] Lowering for VLS truncating stores 2021-07-12 11:14:17 +01:00
sve-fixed-length-trunc.ll
sve-fixed-length-vector-shuffle.ll [AArch64][SVE] Improve fixed length codegen for common vector shuffle case 2021-07-05 12:09:27 +01:00
sve-fmul-idempotency.ll
sve-fold-vscale.ll [SVE][LSR] Teach LSR to enable simple scaled-index addressing mode generation for SVE. 2021-06-14 16:42:34 -07:00
sve-forward-st-to-ld.ll
sve-fp-combine.ll
sve-fp-reduce.ll
sve-fp-rounding.ll
sve-fp.ll
sve-fpext-load.ll
sve-fptrunc-store.ll
sve-gather-scatter-dag-combine.ll
sve-gep.ll
sve-implicit-zero-filling.ll
sve-insert-element.ll [SVE] Added CodeGen support for inserting an element into a predicate vector 2021-06-29 14:55:40 +01:00
sve-insert-vector.ll [TargetLowering][AArch64][SVE] Take into account accessed type when clamping address 2021-06-30 13:30:18 +01:00
sve-insr.ll
sve-int-arith-imm.ll
sve-int-arith-pred.ll
sve-int-arith.ll
sve-int-div-pred.ll
sve-int-imm.ll
sve-int-log-imm.ll
sve-int-log-pred.ll
sve-int-log.ll
sve-int-mad-pred.ll
sve-int-mul-pred.ll
sve-int-mulh-pred.ll
sve-int-pred-reduce.ll
sve-int-reduce-pred.ll
sve-int-reduce.ll
sve-intrinsic-opts-ptest.ll
sve-intrinsics-adr.ll
sve-intrinsics-bfloat.ll
sve-intrinsics-contiguous-prefetches.ll
sve-intrinsics-conversion.ll
sve-intrinsics-counting-bits.ll
sve-intrinsics-counting-elems.ll
sve-intrinsics-create-tuple.ll
sve-intrinsics-dup-x.ll
sve-intrinsics-ff-gather-loads-32bit-scaled-offsets.ll
sve-intrinsics-ff-gather-loads-32bit-unscaled-offsets.ll
sve-intrinsics-ff-gather-loads-64bit-scaled-offset.ll
sve-intrinsics-ff-gather-loads-64bit-unscaled-offset.ll
sve-intrinsics-ff-gather-loads-vector-base-imm-offset.ll
sve-intrinsics-ff-gather-loads-vector-base-scalar-offset.ll
sve-intrinsics-ffr-manipulation.ll
sve-intrinsics-fp-arith-merging.ll
sve-intrinsics-fp-arith.ll
sve-intrinsics-fp-compares.ll [AArch64][SVE] Add ISel patterns for floating point compare with zero instructions 2021-07-08 10:46:12 +00:00
sve-intrinsics-fp-converts.ll
sve-intrinsics-fp-reduce.ll
sve-intrinsics-gather-loads-32bit-scaled-offsets.ll
sve-intrinsics-gather-loads-32bit-unscaled-offsets.ll
sve-intrinsics-gather-loads-64bit-scaled-offset.ll
sve-intrinsics-gather-loads-64bit-unscaled-offset.ll
sve-intrinsics-gather-loads-vector-base-imm-offset.ll
sve-intrinsics-gather-loads-vector-base-scalar-offset.ll
sve-intrinsics-gather-prefetches-scalar-base-vector-indexes.ll
sve-intrinsics-gather-prefetches-vect-base-imm-offset.ll
sve-intrinsics-gather-prefetches-vect-base-invalid-imm-offset.ll
sve-intrinsics-index.ll
sve-intrinsics-insert-extract-tuple.ll
sve-intrinsics-int-arith-imm.ll
sve-intrinsics-int-arith-merging.ll
sve-intrinsics-int-arith.ll
sve-intrinsics-int-compares-with-imm.ll
sve-intrinsics-int-compares.ll
sve-intrinsics-ld1-addressing-mode-reg-imm.ll
sve-intrinsics-ld1-addressing-mode-reg-reg.ll
sve-intrinsics-ld1.ll
sve-intrinsics-ld1ro-addressing-mode-reg-imm.ll
sve-intrinsics-ld1ro-addressing-mode-reg-reg.ll
sve-intrinsics-ld1ro.ll
sve-intrinsics-ldN-reg+imm-addr-mode.ll
sve-intrinsics-ldN-reg+reg-addr-mode.ll
sve-intrinsics-loads-ff.ll
sve-intrinsics-loads-nf.ll
sve-intrinsics-loads.ll
sve-intrinsics-logical-imm.ll
sve-intrinsics-logical.ll
sve-intrinsics-matmul-fp32.ll
sve-intrinsics-matmul-fp64.ll
sve-intrinsics-matmul-int8.ll
sve-intrinsics-perm-select-matmul-fp64.ll
sve-intrinsics-perm-select.ll
sve-intrinsics-pred-creation.ll
sve-intrinsics-pred-operations.ll
sve-intrinsics-pred-testing.ll
sve-intrinsics-reinterpret.ll
sve-intrinsics-reversal.ll
sve-intrinsics-scalar-to-vec.ll
sve-intrinsics-scatter-stores-32bit-scaled-offsets.ll
sve-intrinsics-scatter-stores-32bit-unscaled-offsets.ll
sve-intrinsics-scatter-stores-64bit-scaled-offset.ll
sve-intrinsics-scatter-stores-64bit-unscaled-offset.ll
sve-intrinsics-scatter-stores-vector-base-imm-offset.ll
sve-intrinsics-scatter-stores-vector-base-scalar-offset.ll
sve-intrinsics-sel.ll
sve-intrinsics-shifts-merging.ll
sve-intrinsics-shifts.ll
sve-intrinsics-sqdec.ll
sve-intrinsics-sqinc.ll
sve-intrinsics-st1-addressing-mode-reg-imm.ll
sve-intrinsics-st1-addressing-mode-reg-reg.ll
sve-intrinsics-st1.ll
sve-intrinsics-stN-reg-imm-addr-mode.ll
sve-intrinsics-stN-reg-reg-addr-mode.ll
sve-intrinsics-stores.ll
sve-intrinsics-unpred-form.ll
sve-intrinsics-uqdec.ll
sve-intrinsics-uqinc.ll
sve-intrinsics-while.ll
sve-ld1-addressing-mode-reg-imm.ll
sve-ld1-addressing-mode-reg-reg.ll
sve-ld1r.ll [CodeGen][AArch64][SVE] Use ld1r[bhsd] for vector splat from memory 2021-07-06 12:03:54 +00:00
sve-ld1r.mir [CodeGen][AArch64][SVE] Use ld1r[bhsd] for vector splat from memory 2021-07-06 12:03:54 +00:00
sve-ld-post-inc.ll [CodeGen][AArch64][SVE] Use ld1r[bhsd] for vector splat from memory 2021-07-06 12:03:54 +00:00
sve-localstackalloc.mir
sve-lsr-scaled-index-addressing-mode.ll [SVE][LSR] Teach LSR to enable simple scaled-index addressing mode generation for SVE. 2021-06-14 16:42:34 -07:00
sve-masked-gather-32b-signed-scaled.ll
sve-masked-gather-32b-signed-unscaled.ll
sve-masked-gather-32b-unsigned-scaled.ll
sve-masked-gather-32b-unsigned-unscaled.ll
sve-masked-gather-64b-scaled.ll
sve-masked-gather-64b-unscaled.ll
sve-masked-gather-legalize.ll
sve-masked-gather-vec-plus-imm.ll
sve-masked-gather-vec-plus-reg.ll
sve-masked-gather.ll [AArch64][SVE] Add support for fixed length MSCATTER/MGATHER 2021-07-01 12:13:59 +01:00
sve-masked-ldst-nonext.ll [AArch64][SVE] Fix selection failures for scalable MLOAD nodes with passthru 2021-07-06 14:17:23 +00:00
sve-masked-ldst-sext.ll [AArch64][SVE] Fix selection failures for scalable MLOAD nodes with passthru 2021-07-06 14:17:23 +00:00
sve-masked-ldst-trunc.ll
sve-masked-ldst-zext.ll [AArch64][SVE] Fix selection failures for scalable MLOAD nodes with passthru 2021-07-06 14:17:23 +00:00
sve-masked-scatter-32b-scaled.ll
sve-masked-scatter-32b-unscaled.ll
sve-masked-scatter-64b-scaled.ll
sve-masked-scatter-64b-unscaled.ll
sve-masked-scatter-legalize.ll
sve-masked-scatter-vec-plus-imm.ll
sve-masked-scatter-vec-plus-reg.ll
sve-masked-scatter.ll [SVE] Fixed cast<FixedVectorType> on scalable vector in SelectionDAGBuilder::getUniformBase 2021-07-07 10:48:17 +01:00
sve-merging-stores.ll
sve-mul-idempotency.ll
sve-pred-arith.ll
sve-pred-contiguous-ldst-addressing-mode-reg-imm.ll
sve-pred-contiguous-ldst-addressing-mode-reg-reg.ll
sve-pred-log.ll
sve-pred-non-temporal-ldst-addressing-mode-reg-imm.ll
sve-pred-non-temporal-ldst-addressing-mode-reg-reg.ll
sve-pseudos-expand-undef.mir
sve-ptest-removal-brk.ll
sve-ptest-removal-cmpeq.ll
sve-ptest-removal-cmpeq.mir
sve-ptest-removal-cmpge.ll
sve-ptest-removal-cmpgt.ll
sve-ptest-removal-cmphi.ll
sve-ptest-removal-cmphs.ll
sve-ptest-removal-cmple.ll
sve-ptest-removal-cmplo.ll
sve-ptest-removal-cmpls.ll
sve-ptest-removal-cmplt.ll
sve-ptest-removal-cmpne.ll
sve-ptest-removal-match.ll
sve-ptest-removal-rdffr.mir
sve-ptest-removal-whilege.mir
sve-ptest-removal-whilegt.mir
sve-ptest-removal-whilehi.mir
sve-ptest-removal-whilehs.mir
sve-ptest-removal-whilele.mir
sve-ptest-removal-whilelo.mir
sve-ptest-removal-whilels.mir
sve-ptest-removal-whilelt.mir
sve-ptest-removal-whilerw.mir
sve-ptest-removal-whilewr.mir
sve-redundant-store.ll
sve-rev.ll
sve-select.ll
sve-setcc.ll [AArch64] Remove SETCC of CSEL when the latter's condition can be inverted 2021-06-04 15:53:21 +01:00
sve-sext-zext.ll
sve-split-extract-elt.ll
sve-split-fcvt.ll
sve-split-fp-reduce.ll
sve-split-insert-elt.ll
sve-split-int-pred-reduce.ll
sve-split-int-reduce.ll
sve-split-load.ll
sve-split-store.ll
sve-split-trunc.ll
sve-st1-addressing-mode-reg-imm.ll
sve-st1-addressing-mode-reg-reg.ll
sve-stepvector.ll
sve-tailcall.ll
sve-tbl-dupx.ll
sve-trunc.ll [SVE] Fix PromoteIntRes_TRUNCATE not to call getVectorNumElements 2021-06-16 13:09:43 +01:00
sve-varargs-callee-broken.ll
sve-varargs-caller-broken.ll
sve-varargs.ll
sve-vector-splat.ll [CodeGen][AArch64][SVE] Use ld1r[bhsd] for vector splat from memory 2021-07-06 12:03:54 +00:00
sve-vscale-attr.ll [AArch64][SVE] Wire up vscale_range attribute to SVE min/max vector queries 2021-06-21 13:00:36 +01:00
sve-vscale-combine.ll
sve-vscale.ll [PatternMatch] Make m_VScale compatible with opaque pointers 2021-06-23 23:02:13 +02:00
sve-vselect-imm.ll
sve-widen-scalable-vectortype.ll
sve-zeroinit.ll
swap-compare-operands.ll
swift-async-reg.ll
swift-async-unwind.ll
swift-async.ll
swift-error.ll
swift-return.ll
swiftcc.ll
swifterror.ll [SimplifyCFG] Tail-merging all blocks with ret terminator 2021-06-24 13:15:39 +03:00
swiftself-scavenger.ll
swiftself.ll
swifttail-arm64_32.ll AArch64: use 4-byte slots for arm64_32 pointers in a tail call 2021-07-13 11:08:59 +01:00
swifttail-async.ll
swifttail-call.ll SwiftTailCC: teach verifier musttail rules applicable to this CC. 2021-05-28 11:12:00 +01:00
switch-unreachable-default.ll
tagged-globals-pic.ll
tagged-globals-static.ll
tagp.ll
tail-call-unused-zext.ll
tail-call.ll
tailcall_misched_graph.ll
tailcall-bitcast-memcpy.ll
tailcall-ccmismatch.ll
tailcall-explicit-sret.ll
tailcall-fastisel.ll
tailcall-implicit-sret.ll
tailcall-mem-intrinsics.ll
tailcall-string-rvo.ll
tailcc-notail.ll SwiftTailCC: teach verifier musttail rules applicable to this CC. 2021-05-28 11:12:00 +01:00
tailcc-tail-call.ll
taildup-cfi.ll
taildup-inst-dup-loc.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
tailmerging_in_mbp.ll
tbi.ll
tbz-tbnz.ll
tiny_supported.ll
tiny-model-pic.ll
tiny-model-static.ll
tme.ll
trunc-v1i64.ll
tst-br.ll
uadd_sat_plus.ll
uadd_sat_vec.ll Recommit "[AArch64] Custom lower <4 x i8> loads" 2021-06-30 09:18:06 +01:00
uadd_sat.ll
uaddo.ll
ubsantrap.ll
umulo-128-legalisation-lowering.ll
unfold-masked-merge-scalar-constmask-innerouter.ll
unfold-masked-merge-scalar-constmask-interleavedbits.ll
unfold-masked-merge-scalar-constmask-interleavedbytehalves.ll
unfold-masked-merge-scalar-constmask-lowhigh.ll
unfold-masked-merge-scalar-variablemask.ll
unfold-masked-merge-vector-variablemask-const.ll
unfold-masked-merge-vector-variablemask.ll
unreachable-emergency-spill-slot.mir
unwind-preserved-from-mir.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
unwind-preserved.ll Revert "GlobalISel/AArch64: don't optimize away redundant branches at -O0" 2021-07-09 08:23:36 +05:00
urem-lkk.ll
urem-seteq-illegal-types.ll [AArch64] Remove AArch64ISD::NEG 2021-06-05 19:54:42 +01:00
urem-seteq-nonzero.ll
urem-seteq-optsize.ll
urem-seteq-vec-nonsplat.ll [AArch64] Remove AArch64ISD::NEG 2021-06-05 19:54:42 +01:00
urem-seteq-vec-nonzero.ll
urem-seteq-vec-splat.ll
urem-seteq-vec-tautological.ll
urem-seteq.ll
urem-vector-lkk.ll
use-cr-result-of-dom-icmp-st.ll [SimplifyCFG] Tail-merging all blocks with ret terminator 2021-06-24 13:15:39 +03:00
usub_sat_plus.ll
usub_sat_vec.ll Recommit "[AArch64] Custom lower <4 x i8> loads" 2021-06-30 09:18:06 +01:00
usub_sat.ll
v3f-to-int.ll
v8.5a-neon-frint3264-intrinsic.ll
v8.5a-scalar-frint3264-intrinsic.ll
vararg-tallcall.ll
variant-pcs.ll
vcvt-oversize.ll
vec_cttz.ll
vec_uaddo.ll
vec_umulo.ll
vec-extract-branch.ll [SimplifyCFG] Tail-merging all blocks with ret terminator 2021-06-24 13:15:39 +03:00
vec-libcalls.ll
vecreduce-add-legalization.ll
vecreduce-and-legalization.ll
vecreduce-bool.ll [DAG] Allow isNullOrNullSplat to see truncated zeroes 2021-06-08 10:18:58 +01:00
vecreduce-fadd-legalization-strict.ll
vecreduce-fadd-legalization.ll
vecreduce-fadd.ll
vecreduce-fmax-legalization-nan.ll
vecreduce-fmax-legalization.ll
vecreduce-fmin-legalization.ll
vecreduce-fmul-legalization-strict.ll
vecreduce-propagate-sd-flags.ll
vecreduce-umax-legalization.ll
vector_merge_dep_check.ll
vector_splat-const-shift-of-constmasked.ll
vector-fcopysign.ll [AArch64] Use custom lowering for fp16 vector copysign. 2021-07-02 11:15:30 +01:00
vector-gep.ll
vector-insert-shuffle-cycle.ll
vector-popcnt-128-ult-ugt.ll
vldn_shuffle.ll
vselect-constants.ll
win64_vararg_float_cc.ll
win64_vararg_float.ll
win64_vararg.ll
win64-jumptable.ll
win64-no-uwtable.ll
win64-nocfi.ll
win64cc-backup-x18.ll
win_cst_pool.ll
win-alloca-no-stack-probe.ll
win-alloca.ll
win-catchpad-nested-cxx.ll
win-tls.ll
windows-extern-weak.ll
windows-SEH-support.ll
windows-trap.ll
wineh1.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
wineh2.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
wineh3.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
wineh4.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
wineh5.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
wineh6.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
wineh7.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
wineh8.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
wineh_shrinkwrap.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
wineh-frame0.mir
wineh-frame1.mir
wineh-frame2.mir
wineh-frame3.mir
wineh-frame4.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
wineh-frame5.mir
wineh-frame6.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
wineh-frame7.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
wineh-frame8.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
wineh-frame-predecrement.mir
wineh-frame-scavenge.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
wineh-mingw.ll
wineh-save-lrpair1.mir
wineh-save-lrpair2.mir
wineh-save-lrpair3.mir
wineh-try-catch-cbz.ll
wineh-try-catch-nobase.ll
wineh-try-catch-realign.ll
wineh-try-catch-vla.ll
wineh-try-catch.ll
wineh-unwindhelp-via-fp.ll
wrong_debug_loc_after_regalloc.ll
wrong-callee-save-size-after-livedebugvariables.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
xbfiz.ll
xor.ll
xray-attribute-instrumentation.ll
xray-omit-function-index.ll
xray-partial-instrumentation-skip-entry.ll
xray-partial-instrumentation-skip-exit.ll
xray-tail-call-sled.ll
zero-reg.ll
zext-logic-shift-load.ll
zext-reg-coalesce.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00

++ SVE CodeGen Warnings ++

When the WARN check lines fail in the SVE codegen tests it most likely means you
have introduced a warning due to:
1. Adding an invalid call to VectorType::getNumElements() or EVT::getVectorNumElements()
   when the type is a scalable vector.
2. Relying upon an implicit cast conversion from TypeSize to uint64_t.

For generic code, please modify your code to work with ElementCount and TypeSize directly.
For target-specific code that only deals with fixed-width vectors, use the fixed-size interfaces.
Please refer to the code where those functions live for more details.