2009-09-09 02:09:15 +02:00
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; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
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2012-07-14 01:25:25 +02:00
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; NB: this tests vcnt, vclz, and vcls
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2009-06-23 01:27:02 +02:00
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define <8 x i8> @vcnt8(<8 x i8>* %A) nounwind {
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2013-07-14 08:24:09 +02:00
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;CHECK-LABEL: vcnt8:
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2012-07-18 02:02:16 +02:00
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;CHECK: vcnt.8 {{d[0-9]+}}, {{d[0-9]+}}
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2009-06-23 01:27:02 +02:00
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%tmp1 = load <8 x i8>* %A
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2012-07-18 02:02:16 +02:00
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%tmp2 = call <8 x i8> @llvm.ctpop.v8i8(<8 x i8> %tmp1)
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2009-06-23 01:27:02 +02:00
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ret <8 x i8> %tmp2
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}
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define <16 x i8> @vcntQ8(<16 x i8>* %A) nounwind {
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2013-07-14 08:24:09 +02:00
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;CHECK-LABEL: vcntQ8:
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2012-07-18 02:02:16 +02:00
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;CHECK: vcnt.8 {{q[0-9]+}}, {{q[0-9]+}}
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2009-06-23 01:27:02 +02:00
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%tmp1 = load <16 x i8>* %A
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2012-07-18 02:02:16 +02:00
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%tmp2 = call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %tmp1)
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2009-06-23 01:27:02 +02:00
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ret <16 x i8> %tmp2
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}
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2012-07-18 02:02:16 +02:00
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declare <8 x i8> @llvm.ctpop.v8i8(<8 x i8>) nounwind readnone
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declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8>) nounwind readnone
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2009-10-09 22:20:54 +02:00
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define <8 x i8> @vclz8(<8 x i8>* %A) nounwind {
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2013-07-14 08:24:09 +02:00
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;CHECK-LABEL: vclz8:
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2012-07-14 01:25:25 +02:00
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;CHECK: vclz.i8 {{d[0-9]+}}, {{d[0-9]+}}
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2009-10-09 22:20:54 +02:00
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%tmp1 = load <8 x i8>* %A
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2012-07-14 01:25:25 +02:00
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%tmp2 = call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %tmp1, i1 0)
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2009-10-09 22:20:54 +02:00
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ret <8 x i8> %tmp2
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}
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define <4 x i16> @vclz16(<4 x i16>* %A) nounwind {
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2013-07-14 08:24:09 +02:00
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;CHECK-LABEL: vclz16:
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2012-07-14 01:25:25 +02:00
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;CHECK: vclz.i16 {{d[0-9]+}}, {{d[0-9]+}}
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2009-10-09 22:20:54 +02:00
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%tmp1 = load <4 x i16>* %A
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2012-07-14 01:25:25 +02:00
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%tmp2 = call <4 x i16> @llvm.ctlz.v4i16(<4 x i16> %tmp1, i1 0)
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2009-10-09 22:20:54 +02:00
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @vclz32(<2 x i32>* %A) nounwind {
|
2013-07-14 08:24:09 +02:00
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;CHECK-LABEL: vclz32:
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2012-07-14 01:25:25 +02:00
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;CHECK: vclz.i32 {{d[0-9]+}}, {{d[0-9]+}}
|
2009-10-09 22:20:54 +02:00
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%tmp1 = load <2 x i32>* %A
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2012-07-14 01:25:25 +02:00
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%tmp2 = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %tmp1, i1 0)
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2009-10-09 22:20:54 +02:00
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ret <2 x i32> %tmp2
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}
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define <16 x i8> @vclzQ8(<16 x i8>* %A) nounwind {
|
2013-07-14 08:24:09 +02:00
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;CHECK-LABEL: vclzQ8:
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2012-07-14 01:25:25 +02:00
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;CHECK: vclz.i8 {{q[0-9]+}}, {{q[0-9]+}}
|
2009-10-09 22:20:54 +02:00
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%tmp1 = load <16 x i8>* %A
|
2012-07-14 01:25:25 +02:00
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%tmp2 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %tmp1, i1 0)
|
2009-10-09 22:20:54 +02:00
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|
ret <16 x i8> %tmp2
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|
}
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|
define <8 x i16> @vclzQ16(<8 x i16>* %A) nounwind {
|
2013-07-14 08:24:09 +02:00
|
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|
;CHECK-LABEL: vclzQ16:
|
2012-07-14 01:25:25 +02:00
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;CHECK: vclz.i16 {{q[0-9]+}}, {{q[0-9]+}}
|
2009-10-09 22:20:54 +02:00
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%tmp1 = load <8 x i16>* %A
|
2012-07-14 01:25:25 +02:00
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%tmp2 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %tmp1, i1 0)
|
2009-10-09 22:20:54 +02:00
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|
ret <8 x i16> %tmp2
|
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|
}
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|
define <4 x i32> @vclzQ32(<4 x i32>* %A) nounwind {
|
2013-07-14 08:24:09 +02:00
|
|
|
;CHECK-LABEL: vclzQ32:
|
2012-07-14 01:25:25 +02:00
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;CHECK: vclz.i32 {{q[0-9]+}}, {{q[0-9]+}}
|
2009-10-09 22:20:54 +02:00
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|
%tmp1 = load <4 x i32>* %A
|
2012-07-14 01:25:25 +02:00
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|
%tmp2 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %tmp1, i1 0)
|
2009-10-09 22:20:54 +02:00
|
|
|
ret <4 x i32> %tmp2
|
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|
}
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|
2012-07-14 01:25:25 +02:00
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declare <8 x i8> @llvm.ctlz.v8i8(<8 x i8>, i1) nounwind readnone
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declare <4 x i16> @llvm.ctlz.v4i16(<4 x i16>, i1) nounwind readnone
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declare <2 x i32> @llvm.ctlz.v2i32(<2 x i32>, i1) nounwind readnone
|
2009-10-09 22:20:54 +02:00
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|
2012-07-14 01:25:25 +02:00
|
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|
declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8>, i1) nounwind readnone
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|
declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>, i1) nounwind readnone
|
|
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|
declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1) nounwind readnone
|
2009-10-09 22:20:54 +02:00
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|
|
define <8 x i8> @vclss8(<8 x i8>* %A) nounwind {
|
2013-07-14 08:24:09 +02:00
|
|
|
;CHECK-LABEL: vclss8:
|
2009-10-09 22:20:54 +02:00
|
|
|
;CHECK: vcls.s8
|
|
|
|
%tmp1 = load <8 x i8>* %A
|
|
|
|
%tmp2 = call <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8> %tmp1)
|
|
|
|
ret <8 x i8> %tmp2
|
|
|
|
}
|
|
|
|
|
|
|
|
define <4 x i16> @vclss16(<4 x i16>* %A) nounwind {
|
2013-07-14 08:24:09 +02:00
|
|
|
;CHECK-LABEL: vclss16:
|
2009-10-09 22:20:54 +02:00
|
|
|
;CHECK: vcls.s16
|
|
|
|
%tmp1 = load <4 x i16>* %A
|
|
|
|
%tmp2 = call <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16> %tmp1)
|
|
|
|
ret <4 x i16> %tmp2
|
|
|
|
}
|
|
|
|
|
|
|
|
define <2 x i32> @vclss32(<2 x i32>* %A) nounwind {
|
2013-07-14 08:24:09 +02:00
|
|
|
;CHECK-LABEL: vclss32:
|
2009-10-09 22:20:54 +02:00
|
|
|
;CHECK: vcls.s32
|
|
|
|
%tmp1 = load <2 x i32>* %A
|
|
|
|
%tmp2 = call <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32> %tmp1)
|
|
|
|
ret <2 x i32> %tmp2
|
|
|
|
}
|
|
|
|
|
|
|
|
define <16 x i8> @vclsQs8(<16 x i8>* %A) nounwind {
|
2013-07-14 08:24:09 +02:00
|
|
|
;CHECK-LABEL: vclsQs8:
|
2009-10-09 22:20:54 +02:00
|
|
|
;CHECK: vcls.s8
|
|
|
|
%tmp1 = load <16 x i8>* %A
|
|
|
|
%tmp2 = call <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8> %tmp1)
|
|
|
|
ret <16 x i8> %tmp2
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i16> @vclsQs16(<8 x i16>* %A) nounwind {
|
2013-07-14 08:24:09 +02:00
|
|
|
;CHECK-LABEL: vclsQs16:
|
2009-10-09 22:20:54 +02:00
|
|
|
;CHECK: vcls.s16
|
|
|
|
%tmp1 = load <8 x i16>* %A
|
|
|
|
%tmp2 = call <8 x i16> @llvm.arm.neon.vcls.v8i16(<8 x i16> %tmp1)
|
|
|
|
ret <8 x i16> %tmp2
|
|
|
|
}
|
|
|
|
|
|
|
|
define <4 x i32> @vclsQs32(<4 x i32>* %A) nounwind {
|
2013-07-14 08:24:09 +02:00
|
|
|
;CHECK-LABEL: vclsQs32:
|
2009-10-09 22:20:54 +02:00
|
|
|
;CHECK: vcls.s32
|
|
|
|
%tmp1 = load <4 x i32>* %A
|
|
|
|
%tmp2 = call <4 x i32> @llvm.arm.neon.vcls.v4i32(<4 x i32> %tmp1)
|
|
|
|
ret <4 x i32> %tmp2
|
|
|
|
}
|
|
|
|
|
|
|
|
declare <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8>) nounwind readnone
|
|
|
|
declare <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16>) nounwind readnone
|
|
|
|
declare <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32>) nounwind readnone
|
|
|
|
|
|
|
|
declare <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8>) nounwind readnone
|
|
|
|
declare <8 x i16> @llvm.arm.neon.vcls.v8i16(<8 x i16>) nounwind readnone
|
|
|
|
declare <4 x i32> @llvm.arm.neon.vcls.v4i32(<4 x i32>) nounwind readnone
|