2019-02-27 13:58:48 +00:00
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// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck -check-prefix=GFX9 %s
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2017-02-27 21:04:41 +00:00
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// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s 2>&1 | FileCheck -check-prefix=NOVI %s
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// RUN: not llvm-mc -arch=amdgcn -mcpu=hawaii -show-encoding %s 2>&1 | FileCheck -check-prefix=NOVI %s
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// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s 2>&1 | FileCheck -check-prefix=NOVI %s
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2019-02-27 13:58:48 +00:00
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// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s 2>&1 | FileCheck -check-prefix=NOGFX9 %s
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2017-02-27 21:04:41 +00:00
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v_lshl_add_u32 v1, v2, v3, v4
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// GFX9: v_lshl_add_u32 v1, v2, v3, v4 ; encoding: [0x01,0x00,0xfd,0xd1,0x02,0x07,0x12,0x04]
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// NOVI: :1: error: instruction not supported on this GPU
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v_add_lshl_u32 v1, v2, v3, v4
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// GFX9: v_add_lshl_u32 v1, v2, v3, v4 ; encoding: [0x01,0x00,0xfe,0xd1,0x02,0x07,0x12,0x04]
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// NOVI: :1: error: instruction not supported on this GPU
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v_add3_u32 v1, v2, v3, v4
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// GFX9: v_add3_u32 v1, v2, v3, v4 ; encoding: [0x01,0x00,0xff,0xd1,0x02,0x07,0x12,0x04]
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// NOVI: :1: error: instruction not supported on this GPU
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v_lshl_or_b32 v1, v2, v3, v4
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// GFX9: v_lshl_or_b32 v1, v2, v3, v4 ; encoding: [0x01,0x00,0x00,0xd2,0x02,0x07,0x12,0x04]
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// NOVI: :1: error: instruction not supported on this GPU
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v_and_or_b32 v1, v2, v3, v4
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// GFX9: v_and_or_b32 v1, v2, v3, v4 ; encoding: [0x01,0x00,0x01,0xd2,0x02,0x07,0x12,0x04]
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// NOVI: :1: error: instruction not supported on this GPU
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v_or3_b32 v1, v2, v3, v4
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// GFX9: v_or3_b32 v1, v2, v3, v4 ; encoding: [0x01,0x00,0x02,0xd2,0x02,0x07,0x12,0x04]
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// NOVI: :1: error: instruction not supported on this GPU
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v_pack_b32_f16 v1, v2, v3
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// GFX9: v_pack_b32_f16 v1, v2, v3 ; encoding: [0x01,0x00,0xa0,0xd2,0x02,0x07,0x02,0x00]
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// NOVI: :1: error: instruction not supported on this GPU
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2017-02-27 22:40:39 +00:00
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2017-07-21 13:54:11 +00:00
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v_pack_b32_f16 v5, v1, v2 op_sel:[1,0,0]
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// GFX9: v_pack_b32_f16 v5, v1, v2 op_sel:[1,0,0] ; encoding: [0x05,0x08,0xa0,0xd2,0x01,0x05,0x02,0x00]
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v_pack_b32_f16 v5, v1, v2 op_sel:[0,1,0]
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// GFX9: v_pack_b32_f16 v5, v1, v2 op_sel:[0,1,0] ; encoding: [0x05,0x10,0xa0,0xd2,0x01,0x05,0x02,0x00]
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v_pack_b32_f16 v5, v1, v2 op_sel:[0,0,1]
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// GFX9: v_pack_b32_f16 v5, v1, v2 op_sel:[0,0,1] ; encoding: [0x05,0x40,0xa0,0xd2,0x01,0x05,0x02,0x00]
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2017-02-28 20:27:30 +00:00
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v_xad_u32 v1, v2, v3, v4
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// GFX9: v_xad_u32 v1, v2, v3, v4 ; encoding: [0x01,0x00,0xf3,0xd1,0x02,0x07,0x12,0x04]
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// NOVI: :1: error: instruction not supported on this GPU
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2017-05-17 19:25:06 +00:00
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v_min3_f16 v1, v2, v3, v4
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// GFX9: v_min3_f16 v1, v2, v3, v4 ; encoding: [0x01,0x00,0xf4,0xd1,0x02,0x07,0x12,0x04]
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// NOVI: :1: error: instruction not supported on this GPU
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v_min3_i16 v1, v2, v3, v4
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// GFX9: v_min3_i16 v1, v2, v3, v4 ; encoding: [0x01,0x00,0xf5,0xd1,0x02,0x07,0x12,0x04]
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// NOVI: :1: error: instruction not supported on this GPU
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v_min3_u16 v1, v2, v3, v4
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// GFX9: v_min3_u16 v1, v2, v3, v4 ; encoding: [0x01,0x00,0xf6,0xd1,0x02,0x07,0x12,0x04]
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// NOVI: :1: error: instruction not supported on this GPU
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v_max3_f16 v1, v2, v3, v4
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// GFX9: v_max3_f16 v1, v2, v3, v4 ; encoding: [0x01,0x00,0xf7,0xd1,0x02,0x07,0x12,0x04]
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// NOVI: :1: error: instruction not supported on this GPU
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2017-07-21 13:54:11 +00:00
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v_max3_f16 v5, v1, v2, v3 op_sel:[0,0,0,0]
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// GFX9: v_max3_f16 v5, v1, v2, v3 ; encoding: [0x05,0x00,0xf7,0xd1,0x01,0x05,0x0e,0x04]
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v_max3_f16 v5, v1, v2, v3 op_sel:[1,0,0,0]
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// GFX9: v_max3_f16 v5, v1, v2, v3 op_sel:[1,0,0,0] ; encoding: [0x05,0x08,0xf7,0xd1,0x01,0x05,0x0e,0x04]
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v_max3_f16 v5, v1, v2, v3 op_sel:[0,1,0,0]
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// GFX9: v_max3_f16 v5, v1, v2, v3 op_sel:[0,1,0,0] ; encoding: [0x05,0x10,0xf7,0xd1,0x01,0x05,0x0e,0x04]
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v_max3_f16 v5, v1, v2, v3 op_sel:[0,0,1,0]
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// GFX9: v_max3_f16 v5, v1, v2, v3 op_sel:[0,0,1,0] ; encoding: [0x05,0x20,0xf7,0xd1,0x01,0x05,0x0e,0x04]
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v_max3_f16 v5, v1, v2, v3 op_sel:[0,0,0,1]
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// GFX9: v_max3_f16 v5, v1, v2, v3 op_sel:[0,0,0,1] ; encoding: [0x05,0x40,0xf7,0xd1,0x01,0x05,0x0e,0x04]
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v_max3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1]
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// GFX9: v_max3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1] ; encoding: [0x05,0x78,0xf7,0xd1,0x01,0x05,0x0e,0x04]
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2017-05-17 19:25:06 +00:00
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v_max3_i16 v1, v2, v3, v4
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// GFX9: v_max3_i16 v1, v2, v3, v4 ; encoding: [0x01,0x00,0xf8,0xd1,0x02,0x07,0x12,0x04]
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// NOVI: :1: error: instruction not supported on this GPU
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2017-07-21 13:54:11 +00:00
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v_max3_i16 v5, v1, v2, v3 op_sel:[0,0,0,0]
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// GFX9: v_max3_i16 v5, v1, v2, v3 ; encoding: [0x05,0x00,0xf8,0xd1,0x01,0x05,0x0e,0x04]
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v_max3_i16 v5, v1, v2, v3 op_sel:[1,0,0,0]
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// GFX9: v_max3_i16 v5, v1, v2, v3 op_sel:[1,0,0,0] ; encoding: [0x05,0x08,0xf8,0xd1,0x01,0x05,0x0e,0x04]
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v_max3_i16 v5, v1, v2, v3 op_sel:[0,1,0,0]
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// GFX9: v_max3_i16 v5, v1, v2, v3 op_sel:[0,1,0,0] ; encoding: [0x05,0x10,0xf8,0xd1,0x01,0x05,0x0e,0x04]
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v_max3_i16 v5, v1, v2, v3 op_sel:[0,0,1,0]
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// GFX9: v_max3_i16 v5, v1, v2, v3 op_sel:[0,0,1,0] ; encoding: [0x05,0x20,0xf8,0xd1,0x01,0x05,0x0e,0x04]
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v_max3_i16 v5, v1, v2, v3 op_sel:[0,0,0,1]
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// GFX9: v_max3_i16 v5, v1, v2, v3 op_sel:[0,0,0,1] ; encoding: [0x05,0x40,0xf8,0xd1,0x01,0x05,0x0e,0x04]
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v_max3_i16 v5, v1, v2, v3 op_sel:[1,1,1,1]
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// GFX9: v_max3_i16 v5, v1, v2, v3 op_sel:[1,1,1,1] ; encoding: [0x05,0x78,0xf8,0xd1,0x01,0x05,0x0e,0x04]
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2017-05-17 19:25:06 +00:00
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v_max3_u16 v1, v2, v3, v4
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// GFX9: v_max3_u16 v1, v2, v3, v4 ; encoding: [0x01,0x00,0xf9,0xd1,0x02,0x07,0x12,0x04]
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// NOVI: :1: error: instruction not supported on this GPU
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2017-02-27 22:40:39 +00:00
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v_med3_f16 v1, v2, v3, v4
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// GFX9: v_med3_f16 v1, v2, v3, v4 ; encoding: [0x01,0x00,0xfa,0xd1,0x02,0x07,0x12,0x04]
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// NOVI: :1: error: instruction not supported on this GPU
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v_med3_i16 v1, v2, v3, v4
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// GFX9: v_med3_i16 v1, v2, v3, v4 ; encoding: [0x01,0x00,0xfb,0xd1,0x02,0x07,0x12,0x04]
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// NOVI: :1: error: instruction not supported on this GPU
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v_med3_u16 v1, v2, v3, v4
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// GFX9: v_med3_u16 v1, v2, v3, v4 ; encoding: [0x01,0x00,0xfc,0xd1,0x02,0x07,0x12,0x04]
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// NOVI: :1: error: instruction not supported on this GPU
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2017-07-21 13:54:11 +00:00
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v_mad_u32_u16 v5, v1, v2, v3
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// GFX9: v_mad_u32_u16 v5, v1, v2, v3 ; encoding: [0x05,0x00,0xf1,0xd1,0x01,0x05,0x0e,0x04]
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v_mad_u32_u16 v5, v1, v2, v3 op_sel:[1,0,0,0]
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// GFX9: v_mad_u32_u16 v5, v1, v2, v3 op_sel:[1,0,0,0] ; encoding: [0x05,0x08,0xf1,0xd1,0x01,0x05,0x0e,0x04]
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v_mad_u32_u16 v5, v1, v2, v3 op_sel:[0,1,0,0]
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// GFX9: v_mad_u32_u16 v5, v1, v2, v3 op_sel:[0,1,0,0] ; encoding: [0x05,0x10,0xf1,0xd1,0x01,0x05,0x0e,0x04]
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v_mad_u32_u16 v5, v1, v2, v3 op_sel:[0,0,1,0]
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// GFX9: v_mad_u32_u16 v5, v1, v2, v3 op_sel:[0,0,1,0] ; encoding: [0x05,0x20,0xf1,0xd1,0x01,0x05,0x0e,0x04]
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v_mad_u32_u16 v5, v1, v2, v3 op_sel:[0,0,0,1]
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// GFX9: v_mad_u32_u16 v5, v1, v2, v3 op_sel:[0,0,0,1] ; encoding: [0x05,0x40,0xf1,0xd1,0x01,0x05,0x0e,0x04]
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v_mad_u32_u16 v5, v1, v2, v3 op_sel:[1,1,1,1]
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// GFX9: v_mad_u32_u16 v5, v1, v2, v3 op_sel:[1,1,1,1] ; encoding: [0x05,0x78,0xf1,0xd1,0x01,0x05,0x0e,0x04]
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v_mad_i32_i16 v5, v1, v2, v3
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// GFX9: v_mad_i32_i16 v5, v1, v2, v3 ; encoding: [0x05,0x00,0xf2,0xd1,0x01,0x05,0x0e,0x04]
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v_mad_i32_i16 v5, v1, v2, v3 op_sel:[0,0,0,1]
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// GFX9: v_mad_i32_i16 v5, v1, v2, v3 op_sel:[0,0,0,1] ; encoding: [0x05,0x40,0xf2,0xd1,0x01,0x05,0x0e,0x04]
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v_cvt_pknorm_i16_f16 v5, v1, v2
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// GFX9: v_cvt_pknorm_i16_f16 v5, v1, v2 ; encoding: [0x05,0x00,0x99,0xd2,0x01,0x05,0x02,0x00]
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v_cvt_pknorm_i16_f16 v5, -v1, v2
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// GFX9: v_cvt_pknorm_i16_f16 v5, -v1, v2 ; encoding: [0x05,0x00,0x99,0xd2,0x01,0x05,0x02,0x20]
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v_cvt_pknorm_i16_f16 v5, v1, -v2
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// GFX9: v_cvt_pknorm_i16_f16 v5, v1, -v2 ; encoding: [0x05,0x00,0x99,0xd2,0x01,0x05,0x02,0x40]
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v_cvt_pknorm_i16_f16 v5, -v1, -v2
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// GFX9: v_cvt_pknorm_i16_f16 v5, -v1, -v2 ; encoding: [0x05,0x00,0x99,0xd2,0x01,0x05,0x02,0x60]
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v_cvt_pknorm_i16_f16 v5, |v1|, v2
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// GFX9: v_cvt_pknorm_i16_f16 v5, |v1|, v2 ; encoding: [0x05,0x01,0x99,0xd2,0x01,0x05,0x02,0x00]
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v_cvt_pknorm_i16_f16 v5, v1, |v2|
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// GFX9: v_cvt_pknorm_i16_f16 v5, v1, |v2| ; encoding: [0x05,0x02,0x99,0xd2,0x01,0x05,0x02,0x00]
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v_cvt_pknorm_i16_f16 v5, v1, v2 op_sel:[0,0,0]
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// GFX9: v_cvt_pknorm_i16_f16 v5, v1, v2 ; encoding: [0x05,0x00,0x99,0xd2,0x01,0x05,0x02,0x00]
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v_cvt_pknorm_i16_f16 v5, v1, v2 op_sel:[1,0,0]
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// GFX9: v_cvt_pknorm_i16_f16 v5, v1, v2 op_sel:[1,0,0] ; encoding: [0x05,0x08,0x99,0xd2,0x01,0x05,0x02,0x00]
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v_cvt_pknorm_i16_f16 v5, v1, v2 op_sel:[1,1,1]
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// GFX9: v_cvt_pknorm_i16_f16 v5, v1, v2 op_sel:[1,1,1] ; encoding: [0x05,0x58,0x99,0xd2,0x01,0x05,0x02,0x00]
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v_cvt_pknorm_u16_f16 v5, -v1, -v2
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// GFX9: v_cvt_pknorm_u16_f16 v5, -v1, -v2 ; encoding: [0x05,0x00,0x9a,0xd2,0x01,0x05,0x02,0x60]
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v_cvt_pknorm_u16_f16 v5, |v1|, |v2|
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// GFX9: v_cvt_pknorm_u16_f16 v5, |v1|, |v2| ; encoding: [0x05,0x03,0x9a,0xd2,0x01,0x05,0x02,0x00]
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v_cvt_pknorm_u16_f16 v5, v1, v2 op_sel:[1,1,1]
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// GFX9: v_cvt_pknorm_u16_f16 v5, v1, v2 op_sel:[1,1,1] ; encoding: [0x05,0x58,0x9a,0xd2,0x01,0x05,0x02,0x00]
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v_add_i16 v5, v1, v2
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// GFX9: v_add_i16 v5, v1, v2 ; encoding: [0x05,0x00,0x9e,0xd2,0x01,0x05,0x02,0x00]
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v_add_i16 v5, v1, v2 op_sel:[1,1,1]
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|
// GFX9: v_add_i16 v5, v1, v2 op_sel:[1,1,1] ; encoding: [0x05,0x58,0x9e,0xd2,0x01,0x05,0x02,0x00]
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v_sub_i16 v5, v1, v2
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|
// GFX9: v_sub_i16 v5, v1, v2 ; encoding: [0x05,0x00,0x9f,0xd2,0x01,0x05,0x02,0x00]
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v_sub_i16 v5, v1, v2 op_sel:[1,1,1]
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|
// GFX9: v_sub_i16 v5, v1, v2 op_sel:[1,1,1] ; encoding: [0x05,0x58,0x9f,0xd2,0x01,0x05,0x02,0x00]
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v_sub_i16 v5, v1, v2 clamp
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// GFX9: v_sub_i16 v5, v1, v2 clamp ; encoding: [0x05,0x80,0x9f,0xd2,0x01,0x05,0x02,0x00]
|
2017-08-09 17:10:47 +00:00
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v_fma_f16_e64 v5, v1, v2, v3
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|
// GFX9: v_fma_f16 v5, v1, v2, v3 ; encoding: [0x05,0x00,0x06,0xd2,0x01,0x05,0x0e,0x04]
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v_fma_f16 v5, v1, -v2, v3
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// GFX9: v_fma_f16 v5, v1, -v2, v3 ; encoding: [0x05,0x00,0x06,0xd2,0x01,0x05,0x0e,0x44]
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v_fma_f16 v5, v1, v2, |v3|
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// GFX9: v_fma_f16 v5, v1, v2, |v3| ; encoding: [0x05,0x04,0x06,0xd2,0x01,0x05,0x0e,0x04]
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v_fma_f16 v5, v1, v2, v3 clamp
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// GFX9: v_fma_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0x06,0xd2,0x01,0x05,0x0e,0x04]
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|
2017-08-16 15:16:32 +00:00
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v_fma_f16 v5, v1, v2, v3 op_sel:[1,0,0,0]
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|
// GFX9: v_fma_f16 v5, v1, v2, v3 op_sel:[1,0,0,0] ; encoding: [0x05,0x08,0x06,0xd2,0x01,0x05,0x0e,0x04]
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v_fma_f16 v5, v1, v2, v3 op_sel:[0,1,0,0]
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|
// GFX9: v_fma_f16 v5, v1, v2, v3 op_sel:[0,1,0,0] ; encoding: [0x05,0x10,0x06,0xd2,0x01,0x05,0x0e,0x04]
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v_fma_f16 v5, v1, v2, v3 op_sel:[1,1,1,1]
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|
// GFX9: v_fma_f16 v5, v1, v2, v3 op_sel:[1,1,1,1] ; encoding: [0x05,0x78,0x06,0xd2,0x01,0x05,0x0e,0x04]
|
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|
|
2017-08-09 17:10:47 +00:00
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v_fma_legacy_f16_e64 v5, v1, v2, v3
|
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|
// GFX9: v_fma_legacy_f16 v5, v1, v2, v3 ; encoding: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x04]
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v_fma_legacy_f16 v5, -v1, v2, v3
|
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|
// GFX9: v_fma_legacy_f16 v5, -v1, v2, v3 ; encoding: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x24]
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v_fma_legacy_f16 v5, v1, |v2|, v3
|
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|
// GFX9: v_fma_legacy_f16 v5, v1, |v2|, v3 ; encoding: [0x05,0x02,0xee,0xd1,0x01,0x05,0x0e,0x04]
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v_fma_legacy_f16 v5, v1, v2, v3 clamp
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|
// GFX9: v_fma_legacy_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xee,0xd1,0x01,0x05,0x0e,0x04]
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v_div_fixup_f16_e64 v5, 0.5, v2, v3
|
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|
// GFX9: v_div_fixup_f16 v5, 0.5, v2, v3 ; encoding: [0x05,0x00,0x07,0xd2,0xf0,0x04,0x0e,0x04]
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v_div_fixup_f16 v5, v1, 0.5, v3
|
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|
|
// GFX9: v_div_fixup_f16 v5, v1, 0.5, v3 ; encoding: [0x05,0x00,0x07,0xd2,0x01,0xe1,0x0d,0x04]
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|
v_div_fixup_f16 v5, v1, v2, 0.5
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|
// GFX9: v_div_fixup_f16 v5, v1, v2, 0.5 ; encoding: [0x05,0x00,0x07,0xd2,0x01,0x05,0xc2,0x03]
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v_div_fixup_f16 v5, -v1, v2, v3
|
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|
// GFX9: v_div_fixup_f16 v5, -v1, v2, v3 ; encoding: [0x05,0x00,0x07,0xd2,0x01,0x05,0x0e,0x24]
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v_div_fixup_f16 v5, |v1|, v2, v3
|
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|
// GFX9: v_div_fixup_f16 v5, |v1|, v2, v3 ; encoding: [0x05,0x01,0x07,0xd2,0x01,0x05,0x0e,0x04]
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|
v_div_fixup_f16 v5, v1, v2, v3 clamp
|
|
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|
// GFX9: v_div_fixup_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0x07,0xd2,0x01,0x05,0x0e,0x04]
|
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|
2017-08-16 15:16:32 +00:00
|
|
|
v_div_fixup_f16 v5, v1, v2, v3 op_sel:[1,0,0,0]
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|
// GFX9: v_div_fixup_f16 v5, v1, v2, v3 op_sel:[1,0,0,0] ; encoding: [0x05,0x08,0x07,0xd2,0x01,0x05,0x0e,0x04]
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|
v_div_fixup_f16 v5, v1, v2, v3 op_sel:[0,0,1,0]
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|
// GFX9: v_div_fixup_f16 v5, v1, v2, v3 op_sel:[0,0,1,0] ; encoding: [0x05,0x20,0x07,0xd2,0x01,0x05,0x0e,0x04]
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v_div_fixup_f16 v5, v1, v2, v3 op_sel:[0,0,0,1]
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|
// GFX9: v_div_fixup_f16 v5, v1, v2, v3 op_sel:[0,0,0,1] ; encoding: [0x05,0x40,0x07,0xd2,0x01,0x05,0x0e,0x04]
|
|
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|
|
2017-08-09 17:10:47 +00:00
|
|
|
v_div_fixup_legacy_f16_e64 v5, 0.5, v2, v3
|
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|
|
// GFX9: v_div_fixup_legacy_f16 v5, 0.5, v2, v3 ; encoding: [0x05,0x00,0xef,0xd1,0xf0,0x04,0x0e,0x04]
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v_div_fixup_legacy_f16 v5, v1, 0.5, v3
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|
// GFX9: v_div_fixup_legacy_f16 v5, v1, 0.5, v3 ; encoding: [0x05,0x00,0xef,0xd1,0x01,0xe1,0x0d,0x04]
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v_div_fixup_legacy_f16 v5, v1, v2, 0.5
|
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|
// GFX9: v_div_fixup_legacy_f16 v5, v1, v2, 0.5 ; encoding: [0x05,0x00,0xef,0xd1,0x01,0x05,0xc2,0x03]
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v_div_fixup_legacy_f16 v5, -v1, v2, v3
|
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|
// GFX9: v_div_fixup_legacy_f16 v5, -v1, v2, v3 ; encoding: [0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0x24]
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v_div_fixup_legacy_f16 v5, v1, |v2|, v3
|
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|
// GFX9: v_div_fixup_legacy_f16 v5, v1, |v2|, v3 ; encoding: [0x05,0x02,0xef,0xd1,0x01,0x05,0x0e,0x04]
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|
v_div_fixup_legacy_f16 v5, v1, v2, v3 clamp
|
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|
// GFX9: v_div_fixup_legacy_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xef,0xd1,0x01,0x05,0x0e,0x04]
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|
v_mad_f16_e64 v5, 0.5, v2, v3
|
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|
// GFX9: v_mad_f16 v5, 0.5, v2, v3 ; encoding: [0x05,0x00,0x03,0xd2,0xf0,0x04,0x0e,0x04]
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v_mad_f16 v5, v1, 0.5, v3
|
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|
// GFX9: v_mad_f16 v5, v1, 0.5, v3 ; encoding: [0x05,0x00,0x03,0xd2,0x01,0xe1,0x0d,0x04]
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v_mad_f16 v5, v1, v2, 0.5
|
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|
// GFX9: v_mad_f16 v5, v1, v2, 0.5 ; encoding: [0x05,0x00,0x03,0xd2,0x01,0x05,0xc2,0x03]
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v_mad_f16 v5, v1, v2, -v3
|
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|
// GFX9: v_mad_f16 v5, v1, v2, -v3 ; encoding: [0x05,0x00,0x03,0xd2,0x01,0x05,0x0e,0x84]
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|
v_mad_f16 v5, v1, v2, |v3|
|
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|
// GFX9: v_mad_f16 v5, v1, v2, |v3| ; encoding: [0x05,0x04,0x03,0xd2,0x01,0x05,0x0e,0x04]
|
|
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|
|
|
2017-08-16 15:16:32 +00:00
|
|
|
v_mad_f16 v5, v1, v2, v3 op_sel:[0,0,0,0]
|
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|
|
// GFX9: v_mad_f16 v5, v1, v2, v3 ; encoding: [0x05,0x00,0x03,0xd2,0x01,0x05,0x0e,0x04]
|
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|
v_mad_f16 v5, v1, v2, v3 op_sel:[1,0,0,0]
|
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|
// GFX9: v_mad_f16 v5, v1, v2, v3 op_sel:[1,0,0,0] ; encoding: [0x05,0x08,0x03,0xd2,0x01,0x05,0x0e,0x04]
|
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|
v_mad_f16 v5, v1, v2, v3 op_sel:[0,1,0,0]
|
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|
// GFX9: v_mad_f16 v5, v1, v2, v3 op_sel:[0,1,0,0] ; encoding: [0x05,0x10,0x03,0xd2,0x01,0x05,0x0e,0x04]
|
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|
v_mad_f16 v5, v1, v2, v3 op_sel:[0,0,1,0]
|
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|
// GFX9: v_mad_f16 v5, v1, v2, v3 op_sel:[0,0,1,0] ; encoding: [0x05,0x20,0x03,0xd2,0x01,0x05,0x0e,0x04]
|
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|
|
v_mad_f16 v5, v1, v2, v3 op_sel:[0,0,0,1]
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|
// GFX9: v_mad_f16 v5, v1, v2, v3 op_sel:[0,0,0,1] ; encoding: [0x05,0x40,0x03,0xd2,0x01,0x05,0x0e,0x04]
|
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|
|
v_mad_f16 v5, v1, v2, v3 op_sel:[1,1,1,1]
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|
// GFX9: v_mad_f16 v5, v1, v2, v3 op_sel:[1,1,1,1] ; encoding: [0x05,0x78,0x03,0xd2,0x01,0x05,0x0e,0x04]
|
|
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|
|
|
2017-08-09 17:10:47 +00:00
|
|
|
v_mad_f16 v5, v1, v2, v3 clamp
|
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|
|
// GFX9: v_mad_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0x03,0xd2,0x01,0x05,0x0e,0x04]
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v_mad_i16_e64 v5, 0, v2, v3
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|
// GFX9: v_mad_i16 v5, 0, v2, v3 ; encoding: [0x05,0x00,0x05,0xd2,0x80,0x04,0x0e,0x04]
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v_mad_i16 v5, v1, -1, v3
|
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|
// GFX9: v_mad_i16 v5, v1, -1, v3 ; encoding: [0x05,0x00,0x05,0xd2,0x01,0x83,0x0d,0x04]
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|
v_mad_i16 v5, v1, v2, -4.0
|
AMDGPU: Don't use 16-bit FP inline constants in integer operands
It seems to be a hardware defect that the half inline constants do not
work as expected for the 16-bit integer operations (the inverse does
work correctly). Experimentation seems to show these are really
reading the 32-bit inline constants, which can be observed by writing
inline asm using op_sel to see what's in the high half of the
constant. Theoretically we could fold the high halves of the 32-bit
constants using op_sel.
The *_asm_all.s MC tests are broken, and I don't know where the script
to autogenerate these are. I started manually fixing it, but there's
just too many cases to fix. This also does break the
assembler/disassembler support for these values, and I'm not sure what
to do about it. These are still valid encodings, so it seems like you
should be able to use them in some way. If you wrote assembly using
them, you could have really meant it (perhaps to read the high bits
with op_sel?). The disassembler will print the invalid literal
constant which will fail to re-assemble. The behavior is also
different depending on the use context. Consider this example, which
was previously accepted and encoded using the inline constant:
v_mad_i16 v5, v1, -4.0, v3
; encoding: [0x05,0x00,0xec,0xd1,0x01,0xef,0x0d,0x04]
In contexts where an inline immediate is required (such as on gfx8/9),
this will now be rejected. For gfx10, this will produce the literal
encoding and change the printed format:
v_mad_i16 v5, v1, 0xc400, v3
; encoding: [0x05,0x00,0x5e,0xd7,0x01,0xff,0x0d,0x04,0x00,0xc4,0x00,0x00]
This is just another variation of the issue that we don't perfectly
handle round trip assembly/disassembly due to not tracking how
immediates were encoded. This doesn't matter much in practice, since
compilers don't emit the suboptimal encoding. I doubt any users are
relying on this behavior (although I did make use of the old behavior
to figure out what was wrong).
Fixes bug 46302.
2020-06-14 13:09:02 -04:00
|
|
|
// NOGFX9: invalid literal operand
|
2017-08-09 17:10:47 +00:00
|
|
|
|
2017-08-16 13:51:56 +00:00
|
|
|
v_mad_i16 v5, v1, v2, v3 clamp
|
|
|
|
|
// GFX9: v_mad_i16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0x05,0xd2,0x01,0x05,0x0e,0x04]
|
|
|
|
|
|
2017-08-16 15:16:32 +00:00
|
|
|
v_mad_i16 v5, v1, v2, v3 op_sel:[0,0,0,1]
|
|
|
|
|
// GFX9: v_mad_i16 v5, v1, v2, v3 op_sel:[0,0,0,1] ; encoding: [0x05,0x40,0x05,0xd2,0x01,0x05,0x0e,0x04]
|
|
|
|
|
|
|
|
|
|
v_mad_i16 v5, v1, v2, v3 op_sel:[1,1,1,1]
|
|
|
|
|
// GFX9: v_mad_i16 v5, v1, v2, v3 op_sel:[1,1,1,1] ; encoding: [0x05,0x78,0x05,0xd2,0x01,0x05,0x0e,0x04]
|
|
|
|
|
|
2017-08-09 17:10:47 +00:00
|
|
|
v_mad_legacy_f16_e64 v5, 0.5, v2, v3
|
|
|
|
|
// GFX9: v_mad_legacy_f16 v5, 0.5, v2, v3 ; encoding: [0x05,0x00,0xea,0xd1,0xf0,0x04,0x0e,0x04]
|
|
|
|
|
|
|
|
|
|
v_mad_legacy_f16 v5, v1, 0.5, v3
|
|
|
|
|
// GFX9: v_mad_legacy_f16 v5, v1, 0.5, v3 ; encoding: [0x05,0x00,0xea,0xd1,0x01,0xe1,0x0d,0x04]
|
|
|
|
|
|
|
|
|
|
v_mad_legacy_f16 v5, v1, v2, 0.5
|
|
|
|
|
// GFX9: v_mad_legacy_f16 v5, v1, v2, 0.5 ; encoding: [0x05,0x00,0xea,0xd1,0x01,0x05,0xc2,0x03]
|
|
|
|
|
|
|
|
|
|
v_mad_legacy_f16 v5, v1, -v2, v3
|
|
|
|
|
// GFX9: v_mad_legacy_f16 v5, v1, -v2, v3 ; encoding: [0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0x44]
|
|
|
|
|
|
|
|
|
|
v_mad_legacy_f16 v5, v1, |v2|, v3
|
|
|
|
|
// GFX9: v_mad_legacy_f16 v5, v1, |v2|, v3 ; encoding: [0x05,0x02,0xea,0xd1,0x01,0x05,0x0e,0x04]
|
|
|
|
|
|
|
|
|
|
v_mad_legacy_f16 v5, v1, v2, v3 clamp
|
|
|
|
|
// GFX9: v_mad_legacy_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xea,0xd1,0x01,0x05,0x0e,0x04]
|
|
|
|
|
|
|
|
|
|
v_mad_legacy_i16_e64 v5, 0, v2, v3
|
|
|
|
|
// GFX9: v_mad_legacy_i16 v5, 0, v2, v3 ; encoding: [0x05,0x00,0xec,0xd1,0x80,0x04,0x0e,0x04]
|
|
|
|
|
|
|
|
|
|
v_mad_legacy_i16 v5, v1, -1, v3
|
|
|
|
|
// GFX9: v_mad_legacy_i16 v5, v1, -1, v3 ; encoding: [0x05,0x00,0xec,0xd1,0x01,0x83,0x0d,0x04]
|
|
|
|
|
|
|
|
|
|
v_mad_legacy_i16 v5, v1, v2, -4.0
|
AMDGPU: Don't use 16-bit FP inline constants in integer operands
It seems to be a hardware defect that the half inline constants do not
work as expected for the 16-bit integer operations (the inverse does
work correctly). Experimentation seems to show these are really
reading the 32-bit inline constants, which can be observed by writing
inline asm using op_sel to see what's in the high half of the
constant. Theoretically we could fold the high halves of the 32-bit
constants using op_sel.
The *_asm_all.s MC tests are broken, and I don't know where the script
to autogenerate these are. I started manually fixing it, but there's
just too many cases to fix. This also does break the
assembler/disassembler support for these values, and I'm not sure what
to do about it. These are still valid encodings, so it seems like you
should be able to use them in some way. If you wrote assembly using
them, you could have really meant it (perhaps to read the high bits
with op_sel?). The disassembler will print the invalid literal
constant which will fail to re-assemble. The behavior is also
different depending on the use context. Consider this example, which
was previously accepted and encoded using the inline constant:
v_mad_i16 v5, v1, -4.0, v3
; encoding: [0x05,0x00,0xec,0xd1,0x01,0xef,0x0d,0x04]
In contexts where an inline immediate is required (such as on gfx8/9),
this will now be rejected. For gfx10, this will produce the literal
encoding and change the printed format:
v_mad_i16 v5, v1, 0xc400, v3
; encoding: [0x05,0x00,0x5e,0xd7,0x01,0xff,0x0d,0x04,0x00,0xc4,0x00,0x00]
This is just another variation of the issue that we don't perfectly
handle round trip assembly/disassembly due to not tracking how
immediates were encoded. This doesn't matter much in practice, since
compilers don't emit the suboptimal encoding. I doubt any users are
relying on this behavior (although I did make use of the old behavior
to figure out what was wrong).
Fixes bug 46302.
2020-06-14 13:09:02 -04:00
|
|
|
// NOGFX9: invalid literal operand
|
2017-08-09 17:10:47 +00:00
|
|
|
|
2017-08-16 13:51:56 +00:00
|
|
|
v_mad_legacy_i16 v5, v1, v2, -4.0 clamp
|
AMDGPU: Don't use 16-bit FP inline constants in integer operands
It seems to be a hardware defect that the half inline constants do not
work as expected for the 16-bit integer operations (the inverse does
work correctly). Experimentation seems to show these are really
reading the 32-bit inline constants, which can be observed by writing
inline asm using op_sel to see what's in the high half of the
constant. Theoretically we could fold the high halves of the 32-bit
constants using op_sel.
The *_asm_all.s MC tests are broken, and I don't know where the script
to autogenerate these are. I started manually fixing it, but there's
just too many cases to fix. This also does break the
assembler/disassembler support for these values, and I'm not sure what
to do about it. These are still valid encodings, so it seems like you
should be able to use them in some way. If you wrote assembly using
them, you could have really meant it (perhaps to read the high bits
with op_sel?). The disassembler will print the invalid literal
constant which will fail to re-assemble. The behavior is also
different depending on the use context. Consider this example, which
was previously accepted and encoded using the inline constant:
v_mad_i16 v5, v1, -4.0, v3
; encoding: [0x05,0x00,0xec,0xd1,0x01,0xef,0x0d,0x04]
In contexts where an inline immediate is required (such as on gfx8/9),
this will now be rejected. For gfx10, this will produce the literal
encoding and change the printed format:
v_mad_i16 v5, v1, 0xc400, v3
; encoding: [0x05,0x00,0x5e,0xd7,0x01,0xff,0x0d,0x04,0x00,0xc4,0x00,0x00]
This is just another variation of the issue that we don't perfectly
handle round trip assembly/disassembly due to not tracking how
immediates were encoded. This doesn't matter much in practice, since
compilers don't emit the suboptimal encoding. I doubt any users are
relying on this behavior (although I did make use of the old behavior
to figure out what was wrong).
Fixes bug 46302.
2020-06-14 13:09:02 -04:00
|
|
|
// NOGFX9: invalid literal operand
|
2017-08-16 13:51:56 +00:00
|
|
|
|
2017-08-09 17:10:47 +00:00
|
|
|
v_mad_legacy_u16_e64 v5, 0, v2, v3
|
|
|
|
|
// GFX9: v_mad_legacy_u16 v5, 0, v2, v3 ; encoding: [0x05,0x00,0xeb,0xd1,0x80,0x04,0x0e,0x04]
|
|
|
|
|
|
|
|
|
|
v_mad_legacy_u16 v5, v1, -1, v3
|
|
|
|
|
// GFX9: v_mad_legacy_u16 v5, v1, -1, v3 ; encoding: [0x05,0x00,0xeb,0xd1,0x01,0x83,0x0d,0x04]
|
|
|
|
|
|
|
|
|
|
v_mad_legacy_u16 v5, v1, v2, -4.0
|
AMDGPU: Don't use 16-bit FP inline constants in integer operands
It seems to be a hardware defect that the half inline constants do not
work as expected for the 16-bit integer operations (the inverse does
work correctly). Experimentation seems to show these are really
reading the 32-bit inline constants, which can be observed by writing
inline asm using op_sel to see what's in the high half of the
constant. Theoretically we could fold the high halves of the 32-bit
constants using op_sel.
The *_asm_all.s MC tests are broken, and I don't know where the script
to autogenerate these are. I started manually fixing it, but there's
just too many cases to fix. This also does break the
assembler/disassembler support for these values, and I'm not sure what
to do about it. These are still valid encodings, so it seems like you
should be able to use them in some way. If you wrote assembly using
them, you could have really meant it (perhaps to read the high bits
with op_sel?). The disassembler will print the invalid literal
constant which will fail to re-assemble. The behavior is also
different depending on the use context. Consider this example, which
was previously accepted and encoded using the inline constant:
v_mad_i16 v5, v1, -4.0, v3
; encoding: [0x05,0x00,0xec,0xd1,0x01,0xef,0x0d,0x04]
In contexts where an inline immediate is required (such as on gfx8/9),
this will now be rejected. For gfx10, this will produce the literal
encoding and change the printed format:
v_mad_i16 v5, v1, 0xc400, v3
; encoding: [0x05,0x00,0x5e,0xd7,0x01,0xff,0x0d,0x04,0x00,0xc4,0x00,0x00]
This is just another variation of the issue that we don't perfectly
handle round trip assembly/disassembly due to not tracking how
immediates were encoded. This doesn't matter much in practice, since
compilers don't emit the suboptimal encoding. I doubt any users are
relying on this behavior (although I did make use of the old behavior
to figure out what was wrong).
Fixes bug 46302.
2020-06-14 13:09:02 -04:00
|
|
|
// NOGFX9: invalid literal operand
|
2017-08-09 17:10:47 +00:00
|
|
|
|
2017-08-16 13:51:56 +00:00
|
|
|
v_mad_legacy_u16 v5, v1, v2, -4.0 clamp
|
AMDGPU: Don't use 16-bit FP inline constants in integer operands
It seems to be a hardware defect that the half inline constants do not
work as expected for the 16-bit integer operations (the inverse does
work correctly). Experimentation seems to show these are really
reading the 32-bit inline constants, which can be observed by writing
inline asm using op_sel to see what's in the high half of the
constant. Theoretically we could fold the high halves of the 32-bit
constants using op_sel.
The *_asm_all.s MC tests are broken, and I don't know where the script
to autogenerate these are. I started manually fixing it, but there's
just too many cases to fix. This also does break the
assembler/disassembler support for these values, and I'm not sure what
to do about it. These are still valid encodings, so it seems like you
should be able to use them in some way. If you wrote assembly using
them, you could have really meant it (perhaps to read the high bits
with op_sel?). The disassembler will print the invalid literal
constant which will fail to re-assemble. The behavior is also
different depending on the use context. Consider this example, which
was previously accepted and encoded using the inline constant:
v_mad_i16 v5, v1, -4.0, v3
; encoding: [0x05,0x00,0xec,0xd1,0x01,0xef,0x0d,0x04]
In contexts where an inline immediate is required (such as on gfx8/9),
this will now be rejected. For gfx10, this will produce the literal
encoding and change the printed format:
v_mad_i16 v5, v1, 0xc400, v3
; encoding: [0x05,0x00,0x5e,0xd7,0x01,0xff,0x0d,0x04,0x00,0xc4,0x00,0x00]
This is just another variation of the issue that we don't perfectly
handle round trip assembly/disassembly due to not tracking how
immediates were encoded. This doesn't matter much in practice, since
compilers don't emit the suboptimal encoding. I doubt any users are
relying on this behavior (although I did make use of the old behavior
to figure out what was wrong).
Fixes bug 46302.
2020-06-14 13:09:02 -04:00
|
|
|
// NOGFX9: invalid literal operand
|
2017-08-16 13:51:56 +00:00
|
|
|
|
2017-08-09 17:10:47 +00:00
|
|
|
v_mad_u16_e64 v5, 0, v2, v3
|
|
|
|
|
// GFX9: v_mad_u16 v5, 0, v2, v3 ; encoding: [0x05,0x00,0x04,0xd2,0x80,0x04,0x0e,0x04]
|
|
|
|
|
|
|
|
|
|
v_mad_u16 v5, v1, -1, v3
|
|
|
|
|
// GFX9: v_mad_u16 v5, v1, -1, v3 ; encoding: [0x05,0x00,0x04,0xd2,0x01,0x83,0x0d,0x04]
|
|
|
|
|
|
|
|
|
|
v_mad_u16 v5, v1, v2, -4.0
|
AMDGPU: Don't use 16-bit FP inline constants in integer operands
It seems to be a hardware defect that the half inline constants do not
work as expected for the 16-bit integer operations (the inverse does
work correctly). Experimentation seems to show these are really
reading the 32-bit inline constants, which can be observed by writing
inline asm using op_sel to see what's in the high half of the
constant. Theoretically we could fold the high halves of the 32-bit
constants using op_sel.
The *_asm_all.s MC tests are broken, and I don't know where the script
to autogenerate these are. I started manually fixing it, but there's
just too many cases to fix. This also does break the
assembler/disassembler support for these values, and I'm not sure what
to do about it. These are still valid encodings, so it seems like you
should be able to use them in some way. If you wrote assembly using
them, you could have really meant it (perhaps to read the high bits
with op_sel?). The disassembler will print the invalid literal
constant which will fail to re-assemble. The behavior is also
different depending on the use context. Consider this example, which
was previously accepted and encoded using the inline constant:
v_mad_i16 v5, v1, -4.0, v3
; encoding: [0x05,0x00,0xec,0xd1,0x01,0xef,0x0d,0x04]
In contexts where an inline immediate is required (such as on gfx8/9),
this will now be rejected. For gfx10, this will produce the literal
encoding and change the printed format:
v_mad_i16 v5, v1, 0xc400, v3
; encoding: [0x05,0x00,0x5e,0xd7,0x01,0xff,0x0d,0x04,0x00,0xc4,0x00,0x00]
This is just another variation of the issue that we don't perfectly
handle round trip assembly/disassembly due to not tracking how
immediates were encoded. This doesn't matter much in practice, since
compilers don't emit the suboptimal encoding. I doubt any users are
relying on this behavior (although I did make use of the old behavior
to figure out what was wrong).
Fixes bug 46302.
2020-06-14 13:09:02 -04:00
|
|
|
// NOGFX9: invalid literal operand
|
2017-08-16 13:51:56 +00:00
|
|
|
|
|
|
|
|
v_mad_u16 v5, v1, v2, v3 clamp
|
|
|
|
|
// GFX9: v_mad_u16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0x04,0xd2,0x01,0x05,0x0e,0x04]
|
2017-08-16 15:16:32 +00:00
|
|
|
|
|
|
|
|
v_mad_u16 v5, v1, v2, v3 op_sel:[1,0,0,0]
|
|
|
|
|
// GFX9: v_mad_u16 v5, v1, v2, v3 op_sel:[1,0,0,0] ; encoding: [0x05,0x08,0x04,0xd2,0x01,0x05,0x0e,0x04]
|
|
|
|
|
|
|
|
|
|
v_mad_u16 v5, v1, v2, v3 op_sel:[0,0,0,1]
|
|
|
|
|
// GFX9: v_mad_u16 v5, v1, v2, v3 op_sel:[0,0,0,1] ; encoding: [0x05,0x40,0x04,0xd2,0x01,0x05,0x0e,0x04]
|
|
|
|
|
|
|
|
|
|
v_mad_u16 v5, v1, v2, v3 op_sel:[1,1,1,1]
|
|
|
|
|
// GFX9: v_mad_u16 v5, v1, v2, v3 op_sel:[1,1,1,1] ; encoding: [0x05,0x78,0x04,0xd2,0x01,0x05,0x0e,0x04]
|
2017-11-24 15:37:14 +00:00
|
|
|
|
|
|
|
|
v_interp_p2_f16 v5, v2, attr0.x, v3
|
|
|
|
|
// GFX9: v_interp_p2_f16 v5, v2, attr0.x, v3 ; encoding: [0x05,0x00,0x77,0xd2,0x00,0x04,0x0e,0x04]
|
|
|
|
|
|
|
|
|
|
v_interp_p2_f16 v5, -v2, attr0.x, v3
|
|
|
|
|
// GFX9: v_interp_p2_f16 v5, -v2, attr0.x, v3 ; encoding: [0x05,0x00,0x77,0xd2,0x00,0x04,0x0e,0x44]
|
|
|
|
|
|
|
|
|
|
v_interp_p2_f16 v5, v2, attr0.x, |v3|
|
|
|
|
|
// GFX9: v_interp_p2_f16 v5, v2, attr0.x, |v3| ; encoding: [0x05,0x04,0x77,0xd2,0x00,0x04,0x0e,0x04]
|
|
|
|
|
|
|
|
|
|
v_interp_p2_f16 v5, v2, attr0.w, v3
|
|
|
|
|
// GFX9: v_interp_p2_f16 v5, v2, attr0.w, v3 ; encoding: [0x05,0x00,0x77,0xd2,0xc0,0x04,0x0e,0x04]
|
|
|
|
|
|
|
|
|
|
v_interp_p2_f16 v5, v2, attr0.x, v3 high
|
|
|
|
|
// GFX9: v_interp_p2_f16 v5, v2, attr0.x, v3 high ; encoding: [0x05,0x00,0x77,0xd2,0x00,0x05,0x0e,0x04]
|
|
|
|
|
|
|
|
|
|
v_interp_p2_f16 v5, v2, attr0.x, v3 clamp
|
|
|
|
|
// GFX9: v_interp_p2_f16 v5, v2, attr0.x, v3 clamp ; encoding: [0x05,0x80,0x77,0xd2,0x00,0x04,0x0e,0x04]
|
|
|
|
|
|
|
|
|
|
v_interp_p2_legacy_f16 v5, v2, attr31.x, v3
|
|
|
|
|
// GFX9: v_interp_p2_legacy_f16 v5, v2, attr31.x, v3 ; encoding: [0x05,0x00,0x76,0xd2,0x1f,0x04,0x0e,0x04]
|
|
|
|
|
|
|
|
|
|
v_interp_p2_legacy_f16 v5, -v2, attr0.x, v3
|
|
|
|
|
// GFX9: v_interp_p2_legacy_f16 v5, -v2, attr0.x, v3 ; encoding: [0x05,0x00,0x76,0xd2,0x00,0x04,0x0e,0x44]
|
|
|
|
|
|
|
|
|
|
v_interp_p2_legacy_f16 v5, v2, attr0.x, |v3|
|
|
|
|
|
// GFX9: v_interp_p2_legacy_f16 v5, v2, attr0.x, |v3| ; encoding: [0x05,0x04,0x76,0xd2,0x00,0x04,0x0e,0x04]
|
|
|
|
|
|
|
|
|
|
v_interp_p2_legacy_f16 v5, v2, attr0.w, v3
|
|
|
|
|
// GFX9: v_interp_p2_legacy_f16 v5, v2, attr0.w, v3 ; encoding: [0x05,0x00,0x76,0xd2,0xc0,0x04,0x0e,0x04]
|
|
|
|
|
|
|
|
|
|
v_interp_p2_legacy_f16 v5, v2, attr0.x, v3 high
|
|
|
|
|
// GFX9: v_interp_p2_legacy_f16 v5, v2, attr0.x, v3 high ; encoding: [0x05,0x00,0x76,0xd2,0x00,0x05,0x0e,0x04]
|
|
|
|
|
|
|
|
|
|
v_interp_p2_legacy_f16 v5, v2, attr0.x, v3 clamp
|
|
|
|
|
// GFX9: v_interp_p2_legacy_f16 v5, v2, attr0.x, v3 clamp ; encoding: [0x05,0x80,0x76,0xd2,0x00,0x04,0x0e,0x04]
|
2018-04-02 17:09:20 +00:00
|
|
|
|
|
|
|
|
v_cvt_norm_i16_f16_e64 v5, -v1
|
|
|
|
|
// GFX9: v_cvt_norm_i16_f16_e64 v5, -v1 ; encoding: [0x05,0x00,0x8d,0xd1,0x01,0x01,0x00,0x20]
|
|
|
|
|
// NOVI: error: instruction not supported on this GPU
|
|
|
|
|
|
|
|
|
|
v_cvt_norm_i16_f16_e64 v5, |v1|
|
|
|
|
|
// GFX9: v_cvt_norm_i16_f16_e64 v5, |v1| ; encoding: [0x05,0x01,0x8d,0xd1,0x01,0x01,0x00,0x00]
|
|
|
|
|
// NOVI: error: instruction not supported on this GPU
|
|
|
|
|
|
|
|
|
|
v_cvt_norm_u16_f16_e64 v5, -v1
|
|
|
|
|
// GFX9: v_cvt_norm_u16_f16_e64 v5, -v1 ; encoding: [0x05,0x00,0x8e,0xd1,0x01,0x01,0x00,0x20]
|
|
|
|
|
// NOVI: error: instruction not supported on this GPU
|
|
|
|
|
|
|
|
|
|
v_cvt_norm_u16_f16_e64 v5, |v1|
|
|
|
|
|
// GFX9: v_cvt_norm_u16_f16_e64 v5, |v1| ; encoding: [0x05,0x01,0x8e,0xd1,0x01,0x01,0x00,0x00]
|
|
|
|
|
// NOVI: error: instruction not supported on this GPU
|
|
|
|
|
|
|
|
|
|
v_sat_pk_u8_i16_e64 v5, -1
|
|
|
|
|
// GFX9: v_sat_pk_u8_i16_e64 v5, -1 ; encoding: [0x05,0x00,0x8f,0xd1,0xc1,0x00,0x00,0x00]
|
|
|
|
|
// NOVI: error: instruction not supported on this GPU
|
|
|
|
|
|
|
|
|
|
v_sat_pk_u8_i16_e64 v5, v255
|
|
|
|
|
// GFX9: v_sat_pk_u8_i16_e64 v5, v255 ; encoding: [0x05,0x00,0x8f,0xd1,0xff,0x01,0x00,0x00]
|
|
|
|
|
// NOVI: error: instruction not supported on this GPU
|
2018-04-11 13:13:30 +00:00
|
|
|
|
|
|
|
|
v_screen_partition_4se_b32_e64 v5, v1
|
|
|
|
|
// GXF9: [0x05,0x00,0x77,0xd1,0x01,0x01,0x00,0x00]
|
|
|
|
|
// NOVI: error: instruction not supported on this GPU
|
|
|
|
|
|
|
|
|
|
v_screen_partition_4se_b32_e64 v5, -1
|
|
|
|
|
// GXF9: [0x05,0x00,0x77,0xd1,0xc1,0x00,0x00,0x00]
|
|
|
|
|
// NOVI: error: instruction not supported on this GPU
|
2019-02-27 13:58:48 +00:00
|
|
|
|
2019-03-18 19:35:44 +00:00
|
|
|
v_add_u32 v84, v13, s31 clamp
|
|
|
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// GFX9: v_add_u32_e64 v84, v13, s31 clamp ; encoding: [0x54,0x80,0x34,0xd1,0x0d,0x3f,0x00,0x00]
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// NOVI: error:
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v_sub_u32 v84, v13, s31 clamp
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// GFX9: v_sub_u32_e64 v84, v13, s31 clamp ; encoding: [0x54,0x80,0x35,0xd1,0x0d,0x3f,0x00,0x00]
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// NOVI: error:
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v_subrev_u32 v84, v13, s31 clamp
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// GFX9: v_subrev_u32_e64 v84, v13, s31 clamp ; encoding: [0x54,0x80,0x36,0xd1,0x0d,0x3f,0x00,0x00]
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// NOVI: error:
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v_addc_co_u32 v84, s[4:5], v13, v31, vcc clamp
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// GFX9: v_addc_co_u32_e64 v84, s[4:5], v13, v31, vcc clamp ; encoding: [0x54,0x84,0x1c,0xd1,0x0d,0x3f,0xaa,0x01]
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// NOVI: error:
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v_subb_co_u32 v84, s[2:3], v13, v31, vcc clamp
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// GFX9: v_subb_co_u32_e64 v84, s[2:3], v13, v31, vcc clamp ; encoding: [0x54,0x82,0x1d,0xd1,0x0d,0x3f,0xaa,0x01]
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// NOVI: error:
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v_subbrev_co_u32 v84, vcc, v13, v31, s[6:7] clamp
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// GFX9: v_subbrev_co_u32_e64 v84, vcc, v13, v31, s[6:7] clamp ; encoding: [0x54,0xea,0x1e,0xd1,0x0d,0x3f,0x1a,0x00]
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// NOVI: error:
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v_add_co_u32 v84, s[4:5], v13, v31 clamp
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// GFX9: v_add_co_u32_e64 v84, s[4:5], v13, v31 clamp ; encoding: [0x54,0x84,0x19,0xd1,0x0d,0x3f,0x02,0x00]
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// NOVI: error:
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v_sub_co_u32 v84, s[2:3], v13, v31 clamp
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// GFX9: v_sub_co_u32_e64 v84, s[2:3], v13, v31 clamp ; encoding: [0x54,0x82,0x1a,0xd1,0x0d,0x3f,0x02,0x00]
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// NOVI: error:
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v_subrev_co_u32 v84, vcc, v13, v31 clamp
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// GFX9: v_subrev_co_u32_e64 v84, vcc, v13, v31 clamp ; encoding: [0x54,0xea,0x1b,0xd1,0x0d,0x3f,0x02,0x00]
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// NOVI: error:
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2019-05-14 19:16:24 +00:00
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v_addc_co_u32 v84, vcc, v13, v31, vcc
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// GFX9: v_addc_co_u32_e32 v84, vcc, v13, v31, vcc ; encoding: [0x0d,0x3f,0xa8,0x38]
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// NOVI: error: instruction not supported on this GPU
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v_subb_co_u32 v84, vcc, v13, v31, vcc
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// GFX9: v_subb_co_u32_e32 v84, vcc, v13, v31, vcc ; encoding: [0x0d,0x3f,0xa8,0x3a]
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// NOVI: error: instruction not supported on this GPU
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v_subbrev_co_u32 v84, vcc, v13, v31, vcc
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// GFX9: v_subbrev_co_u32_e32 v84, vcc, v13, v31, vcc ; encoding: [0x0d,0x3f,0xa8,0x3c]
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// NOVI: error: instruction not supported on this GPU
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v_add_co_u32 v84, vcc, v13, v31
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// GFX9: v_add_co_u32_e32 v84, vcc, v13, v31 ; encoding: [0x0d,0x3f,0xa8,0x32]
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// NOVI: error: instruction not supported on this GPU
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v_sub_co_u32 v84, vcc, v13, v31
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// GFX9: v_sub_co_u32_e32 v84, vcc, v13, v31 ; encoding: [0x0d,0x3f,0xa8,0x34]
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// NOVI: error: instruction not supported on this GPU
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v_subrev_co_u32 v84, vcc, v13, v31
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// GFX9: v_subrev_co_u32_e32 v84, vcc, v13, v31 ; encoding: [0x0d,0x3f,0xa8,0x36]
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// NOVI: error: instruction not supported on this GPU
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2020-05-13 14:15:46 +03:00
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v_add_i32 v1, v2, v3
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// GFX9: v_add_i32 v1, v2, v3 ; encoding: [0x01,0x00,0x9c,0xd2,0x02,0x07,0x02,0x00]
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// NOVI: error: instruction not supported on this GPU
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v_add_i32 v1, v2, v3 clamp
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// GFX9: v_add_i32 v1, v2, v3 clamp ; encoding: [0x01,0x80,0x9c,0xd2,0x02,0x07,0x02,0x00]
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// NOVI: error: invalid operand for instruction
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v_sub_i32 v1, v2, v3
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// GFX9: v_sub_i32 v1, v2, v3 ; encoding: [0x01,0x00,0x9d,0xd2,0x02,0x07,0x02,0x00]
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// NOVI: error: instruction not supported on this GPU
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v_sub_i32 v1, v2, v3 clamp
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// GFX9: v_sub_i32 v1, v2, v3 clamp ; encoding: [0x01,0x80,0x9d,0xd2,0x02,0x07,0x02,0x00]
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// NOVI: error: invalid operand for instruction
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2019-02-27 13:58:48 +00:00
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//===----------------------------------------------------------------------===//
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// Validate register size checks (bug 37943)
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//===----------------------------------------------------------------------===//
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// NOVI: error: invalid operand for instruction
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// NOGFX9: error: invalid operand for instruction
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v_add_f64 v[0:1], s0, v[0:1]
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// NOVI: error: invalid operand for instruction
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// NOGFX9: error: invalid operand for instruction
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v_add_f64 v[0:1], s[0:3], v[0:1]
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// NOVI: error: invalid operand for instruction
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// NOGFX9: error: invalid operand for instruction
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v_add_f64 v[0:1], v0, v[0:1]
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// NOVI: error: invalid operand for instruction
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// NOGFX9: error: invalid operand for instruction
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v_add_f64 v[0:1], v[0:2], v[0:1]
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// NOVI: error: invalid operand for instruction
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// NOGFX9: error: invalid operand for instruction
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v_add_f64 v[0:1], v[0:3], v[0:1]
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// NOVI: error: invalid operand for instruction
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// NOGFX9: error: invalid operand for instruction
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v_add_f64 v[0:1], v[0:1], v0
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// NOVI: error: invalid operand for instruction
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// NOGFX9: error: invalid operand for instruction
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v_add_f64 v[0:1], v[0:1], s0
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// NOVI: error: invalid operand for instruction
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// NOGFX9: error: invalid operand for instruction
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v_add_f32 v0, s[0:1], v0
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// NOVI: error: invalid operand for instruction
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// NOGFX9: error: invalid operand for instruction
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v_add_f32 v0, v[0:1], v0
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// NOVI: error: invalid operand for instruction
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// NOGFX9: error: invalid operand for instruction
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v_add_f32 v0, v0, s[0:1]
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|
// NOVI: error: invalid operand for instruction
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|
// NOGFX9: error: invalid operand for instruction
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v_add_f32 v0, v0, v[0:1]
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|
// NOVI: error: invalid operand for instruction
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|
// NOGFX9: error: invalid operand for instruction
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|
|
v_add_f16 v0, s[0:1], v0
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|
// NOVI: error: invalid operand for instruction
|
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|
// NOGFX9: error: invalid operand for instruction
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|
|
v_add_f16 v0, v[0:1], v0
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|
// NOVI: error: invalid operand for instruction
|
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|
// NOGFX9: error: invalid operand for instruction
|
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|
|
v_add_f16 v0, v0, s[0:1]
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|
// NOVI: error: invalid operand for instruction
|
|
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|
|
// NOGFX9: error: invalid operand for instruction
|
|
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|
|
v_add_f16 v0, v0, v[0:1]
|
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|
// NOVI: error: invalid operand for instruction
|
|
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|
|
// NOGFX9: error: invalid operand for instruction
|
|
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|
|
v_add_u16 v0, s[0:1], v0
|
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|
// NOVI: error: invalid operand for instruction
|
|
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|
|
// NOGFX9: error: invalid operand for instruction
|
|
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|
|
v_add_u16 v0, v[0:1], v0
|
|
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|
|
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|
|
// NOVI: error: invalid operand for instruction
|
|
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|
|
// NOGFX9: error: invalid operand for instruction
|
|
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|
|
v_add_u16 v0, v0, s[0:1]
|
|
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|
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|
|
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|
|
// NOVI: error: invalid operand for instruction
|
|
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|
|
// NOGFX9: error: invalid operand for instruction
|
|
|
|
|
v_add_u16 v0, v0, v[0:1]
|
2019-03-18 19:35:44 +00:00
|
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