2014-05-24 14:50:23 +02:00
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//===-- AArch64Subtarget.cpp - AArch64 Subtarget Information ----*- C++ -*-===//
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2014-03-29 11:18:08 +01:00
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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2014-05-24 14:50:23 +02:00
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// This file implements the AArch64 specific subclass of TargetSubtarget.
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2014-03-29 11:18:08 +01:00
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//
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//===----------------------------------------------------------------------===//
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2016-05-25 23:37:29 +02:00
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#include "AArch64Subtarget.h"
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2017-05-01 23:53:19 +02:00
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#include "AArch64.h"
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2014-05-24 14:50:23 +02:00
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#include "AArch64InstrInfo.h"
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2014-10-09 20:20:51 +02:00
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#include "AArch64PBQPRegAlloc.h"
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2017-05-01 23:53:19 +02:00
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#include "AArch64TargetMachine.h"
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#include "AArch64CallLowering.h"
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#include "AArch64LegalizerInfo.h"
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#include "AArch64RegisterBankInfo.h"
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#include "llvm/CodeGen/GlobalISel/IRTranslator.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
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#include "llvm/CodeGen/GlobalISel/Legalizer.h"
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#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
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2014-03-29 11:18:08 +01:00
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#include "llvm/CodeGen/MachineScheduler.h"
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#include "llvm/IR/GlobalValue.h"
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#include "llvm/Support/TargetRegistry.h"
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2014-04-22 04:03:14 +02:00
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using namespace llvm;
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2014-05-24 14:50:23 +02:00
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#define DEBUG_TYPE "aarch64-subtarget"
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2014-04-22 00:55:11 +02:00
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2014-03-29 11:18:08 +01:00
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#define GET_SUBTARGETINFO_CTOR
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#define GET_SUBTARGETINFO_TARGET_DESC
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2014-05-24 14:50:23 +02:00
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#include "AArch64GenSubtargetInfo.inc"
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2014-03-29 11:18:08 +01:00
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2014-05-22 01:40:26 +02:00
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static cl::opt<bool>
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2014-05-24 14:50:23 +02:00
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EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if "
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2014-05-22 01:40:26 +02:00
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"converter pass"), cl::init(true), cl::Hidden);
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2015-11-10 01:44:23 +01:00
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// If OS supports TBI, use this flag to enable it.
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static cl::opt<bool>
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UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of "
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"an address is ignored"), cl::init(false), cl::Hidden);
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2017-04-17 20:18:47 +02:00
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static cl::opt<bool>
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UseNonLazyBind("aarch64-enable-nonlazybind",
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cl::desc("Call nonlazybind functions via direct GOT load"),
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cl::init(false), cl::Hidden);
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2014-06-11 02:46:34 +02:00
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AArch64Subtarget &
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2016-10-03 22:17:02 +02:00
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AArch64Subtarget::initializeSubtargetDependencies(StringRef FS,
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StringRef CPUString) {
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2014-06-11 02:46:34 +02:00
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// Determine default and user-specified characteristics
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if (CPUString.empty())
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CPUString = "generic";
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ParseSubtargetFeatures(CPUString, FS);
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2016-06-02 20:03:53 +02:00
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initializeProperties();
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2014-06-11 02:46:34 +02:00
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return *this;
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}
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2016-06-02 20:03:53 +02:00
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void AArch64Subtarget::initializeProperties() {
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// Initialize CPU specific properties. We should add a tablegen feature for
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// this in the future so we can specify it together with the subtarget
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// features.
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switch (ARMProcFamily) {
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case Cyclone:
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CacheLineSize = 64;
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PrefetchDistance = 280;
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MinPrefetchStride = 2048;
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MaxPrefetchIterationsAhead = 3;
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break;
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case CortexA57:
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MaxInterleaveFactor = 4;
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2017-07-07 12:43:01 +02:00
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PrefFunctionAlignment = 4;
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2016-06-02 20:03:53 +02:00
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break;
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2016-06-10 18:00:18 +02:00
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case ExynosM1:
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2016-10-21 18:28:27 +02:00
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MaxInterleaveFactor = 4;
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2016-10-25 22:05:42 +02:00
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MaxJumpTableSize = 8;
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2016-06-10 18:00:18 +02:00
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PrefFunctionAlignment = 4;
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PrefLoopAlignment = 3;
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break;
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2016-11-22 15:25:02 +01:00
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case Falkor:
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MaxInterleaveFactor = 4;
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2017-05-15 23:15:01 +02:00
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// FIXME: remove this to enable 64-bit SLP if performance looks good.
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MinVectorRegisterBitWidth = 128;
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2017-06-12 18:34:19 +02:00
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CacheLineSize = 128;
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PrefetchDistance = 820;
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MinPrefetchStride = 2048;
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MaxPrefetchIterationsAhead = 8;
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2016-11-22 15:25:02 +01:00
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break;
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2016-06-02 20:03:53 +02:00
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case Kryo:
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MaxInterleaveFactor = 4;
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VectorInsertExtractBaseCost = 2;
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2016-06-22 00:47:56 +02:00
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CacheLineSize = 128;
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PrefetchDistance = 740;
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MinPrefetchStride = 1024;
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MaxPrefetchIterationsAhead = 11;
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2017-05-15 23:15:01 +02:00
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// FIXME: remove this to enable 64-bit SLP if performance looks good.
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MinVectorRegisterBitWidth = 128;
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2016-06-02 20:03:53 +02:00
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break;
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2017-03-07 20:42:40 +01:00
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case ThunderX2T99:
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CacheLineSize = 64;
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PrefFunctionAlignment = 3;
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PrefLoopAlignment = 2;
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2016-06-30 08:42:31 +02:00
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MaxInterleaveFactor = 4;
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2017-03-07 20:42:40 +01:00
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PrefetchDistance = 128;
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MinPrefetchStride = 1024;
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MaxPrefetchIterationsAhead = 4;
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2017-05-15 23:15:01 +02:00
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// FIXME: remove this to enable 64-bit SLP if performance looks good.
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MinVectorRegisterBitWidth = 128;
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2016-06-30 08:42:31 +02:00
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break;
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2017-02-17 19:34:24 +01:00
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case ThunderX:
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case ThunderXT88:
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case ThunderXT81:
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case ThunderXT83:
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CacheLineSize = 128;
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2017-03-07 20:42:40 +01:00
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PrefFunctionAlignment = 3;
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PrefLoopAlignment = 2;
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2017-05-15 23:15:01 +02:00
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// FIXME: remove this to enable 64-bit SLP if performance looks good.
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MinVectorRegisterBitWidth = 128;
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2017-02-17 19:34:24 +01:00
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break;
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2016-06-02 20:03:53 +02:00
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case CortexA35: break;
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[AArch64] Use 8 bytes as preferred function alignment on Cortex-A53.
Summary:
This change gives a 0.25% speedup on execution time, a 0.82% improvement
in benchmark scores and a 0.20% increase in binary size on a Cortex-A53.
These numbers are the geomean results on a wide range of benchmarks from
the test-suite and a range of proprietary suites.
Reviewers: t.p.northover, aadg, silviu.baranga, mcrosier, rengolin
Reviewed By: rengolin
Subscribers: grimar, davide, aemerson, rengolin, javed.absar, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D35568
llvm-svn: 309494
2017-07-29 22:04:54 +02:00
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case CortexA53:
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PrefFunctionAlignment = 3;
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break;
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2017-08-21 10:43:06 +02:00
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case CortexA55: break;
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2017-07-07 12:15:49 +02:00
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case CortexA72:
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2017-07-18 11:31:18 +02:00
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case CortexA73:
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2017-08-21 10:43:06 +02:00
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case CortexA75:
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2017-07-18 11:31:18 +02:00
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PrefFunctionAlignment = 4;
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break;
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2016-06-10 18:00:18 +02:00
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case Others: break;
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2016-06-02 20:03:53 +02:00
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}
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}
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2015-06-10 14:11:26 +02:00
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AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
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2014-10-03 02:42:41 +02:00
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const std::string &FS,
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2017-05-19 13:08:33 +02:00
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const TargetMachine &TM, bool LittleEndian)
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2017-07-18 22:41:33 +02:00
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: AArch64GenSubtargetInfo(TT, CPU, FS),
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2017-08-16 00:31:51 +02:00
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ReserveX18(TT.isOSDarwin() || TT.isOSWindows()), IsLittle(LittleEndian),
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TargetTriple(TT), FrameLowering(),
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2016-10-03 22:17:02 +02:00
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InstrInfo(initializeSubtargetDependencies(FS, CPU)), TSInfo(),
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2017-08-16 00:31:51 +02:00
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TLInfo(TM, *this) {
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CallLoweringInfo.reset(new AArch64CallLowering(*getTargetLowering()));
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Legalizer.reset(new AArch64LegalizerInfo());
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2017-05-01 23:53:19 +02:00
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auto *RBI = new AArch64RegisterBankInfo(*getRegisterInfo());
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// FIXME: At this point, we can't rely on Subtarget having RBI.
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// It's awkward to mix passing RBI and the Subtarget; should we pass
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// TII/TRI as well?
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2017-08-16 00:31:51 +02:00
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InstSelector.reset(createAArch64InstructionSelector(
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2017-05-01 23:53:19 +02:00
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*static_cast<const AArch64TargetMachine *>(&TM), *this, *RBI));
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2017-08-16 00:31:51 +02:00
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RegBankInfo.reset(RBI);
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2017-05-01 23:53:19 +02:00
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}
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2016-02-16 20:26:02 +01:00
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const CallLowering *AArch64Subtarget::getCallLowering() const {
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2017-08-16 00:31:51 +02:00
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return CallLoweringInfo.get();
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2016-04-06 19:26:03 +02:00
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}
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2016-07-27 16:31:55 +02:00
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const InstructionSelector *AArch64Subtarget::getInstructionSelector() const {
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2017-08-16 00:31:51 +02:00
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return InstSelector.get();
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2016-07-27 16:31:55 +02:00
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}
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2016-10-15 00:18:18 +02:00
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const LegalizerInfo *AArch64Subtarget::getLegalizerInfo() const {
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2017-08-16 00:31:51 +02:00
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return Legalizer.get();
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2016-07-22 22:03:43 +02:00
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}
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2016-04-06 19:26:03 +02:00
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const RegisterBankInfo *AArch64Subtarget::getRegBankInfo() const {
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2017-08-16 00:31:51 +02:00
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return RegBankInfo.get();
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2016-02-16 20:26:02 +01:00
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}
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2014-03-29 11:18:08 +01:00
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2016-05-26 00:44:06 +02:00
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/// Find the target operand flags that describe how a global value should be
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/// referenced for the current subtarget.
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2014-03-29 11:18:08 +01:00
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unsigned char
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2014-05-24 14:50:23 +02:00
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AArch64Subtarget::ClassifyGlobalReference(const GlobalValue *GV,
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2016-05-26 00:44:06 +02:00
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const TargetMachine &TM) const {
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2014-04-02 16:39:11 +02:00
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// MachO large model always goes via a GOT, simply to get a single 8-byte
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// absolute relocation on all global addresses.
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if (TM.getCodeModel() == CodeModel::Large && isTargetMachO())
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2014-05-24 14:50:23 +02:00
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return AArch64II::MO_GOT;
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2014-03-29 11:18:08 +01:00
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2016-06-28 01:15:57 +02:00
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if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
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2016-05-26 14:42:55 +02:00
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return AArch64II::MO_GOT;
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2017-04-04 21:51:53 +02:00
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// The small code model's direct accesses use ADRP, which cannot
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// necessarily produce the value 0 (if the code is above 4GB).
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if (useSmallAddressing() && GV->hasExternalWeakLinkage())
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2016-05-31 20:31:14 +02:00
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return AArch64II::MO_GOT;
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2014-03-29 11:18:08 +01:00
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2014-05-24 14:50:23 +02:00
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return AArch64II::MO_NO_FLAG;
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2014-03-29 11:18:08 +01:00
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}
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2017-04-17 19:27:56 +02:00
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unsigned char AArch64Subtarget::classifyGlobalFunctionReference(
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const GlobalValue *GV, const TargetMachine &TM) const {
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// MachO large model always goes via a GOT, because we don't have the
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// relocations available to do anything else..
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if (TM.getCodeModel() == CodeModel::Large && isTargetMachO() &&
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!GV->hasInternalLinkage())
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return AArch64II::MO_GOT;
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// NonLazyBind goes via GOT unless we know it's available locally.
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auto *F = dyn_cast<Function>(GV);
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2017-04-17 20:18:47 +02:00
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if (UseNonLazyBind && F && F->hasFnAttribute(Attribute::NonLazyBind) &&
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2017-04-17 19:27:56 +02:00
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!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
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return AArch64II::MO_GOT;
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return AArch64II::MO_NO_FLAG;
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}
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2014-03-29 11:18:08 +01:00
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/// This function returns the name of a function which has an interface
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/// like the non-standard bzero function, if such a function exists on
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/// the current subtarget and it is considered prefereable over
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/// memset with zero passed as the second argument. Otherwise it
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/// returns null.
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2014-05-24 14:50:23 +02:00
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const char *AArch64Subtarget::getBZeroEntry() const {
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2014-05-01 15:11:59 +02:00
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// Prefer bzero on Darwin only.
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if(isTargetDarwin())
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return "bzero";
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return nullptr;
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2014-03-29 11:18:08 +01:00
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}
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2014-05-24 14:50:23 +02:00
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void AArch64Subtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
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2016-07-01 02:23:27 +02:00
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unsigned NumRegionInstrs) const {
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2014-03-29 11:18:08 +01:00
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// LNT run (at least on Cyclone) showed reasonably significant gains for
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// bi-directional scheduling. 253.perlbmk.
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Policy.OnlyTopDown = false;
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Policy.OnlyBottomUp = false;
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2015-10-22 20:07:38 +02:00
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// Enabling or Disabling the latency heuristic is a close call: It seems to
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// help nearly no benchmark on out-of-order architectures, on the other hand
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// it regresses register pressure on a few benchmarking.
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2016-06-02 20:03:53 +02:00
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Policy.DisableLatencyHeuristic = DisableLatencySchedHeuristic;
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2014-03-29 11:18:08 +01:00
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}
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2014-05-22 01:40:26 +02:00
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2014-05-24 14:50:23 +02:00
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bool AArch64Subtarget::enableEarlyIfConversion() const {
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2014-05-22 01:40:26 +02:00
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return EnableEarlyIfConvert;
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}
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2014-10-09 20:20:51 +02:00
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2015-11-10 01:44:23 +01:00
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bool AArch64Subtarget::supportsAddressTopByteIgnored() const {
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if (!UseAddressTopByteIgnored)
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return false;
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if (TargetTriple.isiOS()) {
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unsigned Major, Minor, Micro;
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TargetTriple.getiOSVersion(Major, Minor, Micro);
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return Major >= 8;
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}
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return false;
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}
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2014-10-09 20:20:51 +02:00
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std::unique_ptr<PBQPRAConstraint>
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AArch64Subtarget::getCustomPBQPConstraints() const {
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2016-06-02 20:03:53 +02:00
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return balanceFPOps() ? llvm::make_unique<A57ChainingConstraint>() : nullptr;
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2014-10-09 20:20:51 +02:00
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}
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