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llvm-mirror/test/CodeGen/RISCV/double-stack-spill-restore.ll

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[RISCV] Add tests missed in r329871 llvm-svn: 329872
2018-04-12 07:36:44 +02:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IFD %s
[RISCV] Implement RV64D codegen This patch: * Adds necessary RV64D codegen patterns * Modifies CC_RISCV so it will properly handle f64 types (with soft float ABI) Note that in general there is no reason to try to select fcvt.w[u].d rather than fcvt.l[u].d for i32 conversions because fptosi/fptoui produce poison if the input won't fit into the target type. Differential Revision: https://reviews.llvm.org/D53237 llvm-svn: 352833
2019-02-01 04:53:30 +01:00
; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IFD %s
[RISCV] Add tests missed in r329871 llvm-svn: 329872
2018-04-12 07:36:44 +02:00
define double @func(double %d, i32 %n) nounwind {
; RV32IFD-LABEL: func:
; RV32IFD: # %bb.0: # %entry
; RV32IFD-NEXT: addi sp, sp, -32
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-09 20:41:19 +01:00
; RV32IFD-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
[RISCV] Add tests missed in r329871 llvm-svn: 329872
2018-04-12 07:36:44 +02:00
; RV32IFD-NEXT: sw a0, 16(sp)
; RV32IFD-NEXT: sw a1, 20(sp)
; RV32IFD-NEXT: fld ft0, 16(sp)
; RV32IFD-NEXT: beqz a2, .LBB0_2
; RV32IFD-NEXT: # %bb.1: # %if.else
; RV32IFD-NEXT: addi a2, a2, -1
; RV32IFD-NEXT: fsd ft0, 16(sp)
; RV32IFD-NEXT: lw a0, 16(sp)
; RV32IFD-NEXT: lw a1, 20(sp)
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-09 20:41:19 +01:00
; RV32IFD-NEXT: fsd ft0, 8(sp) # 8-byte Folded Spill
[TargetLowering][RISCV] Don't transform (seteq/ne (sext_inreg X, VT), C1) -> (seteq/ne (zext_inreg X, VT), C1) if the sext_inreg is cheaper RISCV has to use 2 shifts for (i64 (zext_inreg X, i32)), but we can use addiw rd, rs1, x0 for sext_inreg. We already understood this when type legalizing i32 seteq/ne on rv64. But this transform in SimplifySetCC would sometimes undo it. Reviewed By: luismarques Differential Revision: https://reviews.llvm.org/D95289
2021-01-26 01:17:42 +01:00
; RV32IFD-NEXT: call func@plt
[RISCV] Add tests missed in r329871 llvm-svn: 329872
2018-04-12 07:36:44 +02:00
; RV32IFD-NEXT: sw a0, 16(sp)
; RV32IFD-NEXT: sw a1, 20(sp)
; RV32IFD-NEXT: fld ft0, 16(sp)
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-09 20:41:19 +01:00
; RV32IFD-NEXT: fld ft1, 8(sp) # 8-byte Folded Reload
[RISCV] Add tests missed in r329871 llvm-svn: 329872
2018-04-12 07:36:44 +02:00
; RV32IFD-NEXT: fadd.d ft0, ft0, ft1
; RV32IFD-NEXT: .LBB0_2: # %return
; RV32IFD-NEXT: fsd ft0, 16(sp)
; RV32IFD-NEXT: lw a0, 16(sp)
; RV32IFD-NEXT: lw a1, 20(sp)
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-09 20:41:19 +01:00
; RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
[RISCV] Add tests missed in r329871 llvm-svn: 329872
2018-04-12 07:36:44 +02:00
; RV32IFD-NEXT: addi sp, sp, 32
; RV32IFD-NEXT: ret
[RISCV] Implement RV64D codegen This patch: * Adds necessary RV64D codegen patterns * Modifies CC_RISCV so it will properly handle f64 types (with soft float ABI) Note that in general there is no reason to try to select fcvt.w[u].d rather than fcvt.l[u].d for i32 conversions because fptosi/fptoui produce poison if the input won't fit into the target type. Differential Revision: https://reviews.llvm.org/D53237 llvm-svn: 352833
2019-02-01 04:53:30 +01:00
;
; RV64IFD-LABEL: func:
; RV64IFD: # %bb.0: # %entry
; RV64IFD-NEXT: addi sp, sp, -16
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-09 20:41:19 +01:00
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
[TargetLowering][RISCV] Don't transform (seteq/ne (sext_inreg X, VT), C1) -> (seteq/ne (zext_inreg X, VT), C1) if the sext_inreg is cheaper RISCV has to use 2 shifts for (i64 (zext_inreg X, i32)), but we can use addiw rd, rs1, x0 for sext_inreg. We already understood this when type legalizing i32 seteq/ne on rv64. But this transform in SimplifySetCC would sometimes undo it. Reviewed By: luismarques Differential Revision: https://reviews.llvm.org/D95289
2021-01-26 01:17:42 +01:00
; RV64IFD-NEXT: sext.w a2, a1
[RISCV] Implement RV64D codegen This patch: * Adds necessary RV64D codegen patterns * Modifies CC_RISCV so it will properly handle f64 types (with soft float ABI) Note that in general there is no reason to try to select fcvt.w[u].d rather than fcvt.l[u].d for i32 conversions because fptosi/fptoui produce poison if the input won't fit into the target type. Differential Revision: https://reviews.llvm.org/D53237 llvm-svn: 352833
2019-02-01 04:53:30 +01:00
; RV64IFD-NEXT: fmv.d.x ft0, a0
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 13:15:35 +02:00
; RV64IFD-NEXT: beqz a2, .LBB0_2
[RISCV] Implement RV64D codegen This patch: * Adds necessary RV64D codegen patterns * Modifies CC_RISCV so it will properly handle f64 types (with soft float ABI) Note that in general there is no reason to try to select fcvt.w[u].d rather than fcvt.l[u].d for i32 conversions because fptosi/fptoui produce poison if the input won't fit into the target type. Differential Revision: https://reviews.llvm.org/D53237 llvm-svn: 352833
2019-02-01 04:53:30 +01:00
; RV64IFD-NEXT: # %bb.1: # %if.else
; RV64IFD-NEXT: addi a1, a1, -1
; RV64IFD-NEXT: fmv.x.d a0, ft0
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-09 20:41:19 +01:00
; RV64IFD-NEXT: fsd ft0, 0(sp) # 8-byte Folded Spill
[TargetLowering][RISCV] Don't transform (seteq/ne (sext_inreg X, VT), C1) -> (seteq/ne (zext_inreg X, VT), C1) if the sext_inreg is cheaper RISCV has to use 2 shifts for (i64 (zext_inreg X, i32)), but we can use addiw rd, rs1, x0 for sext_inreg. We already understood this when type legalizing i32 seteq/ne on rv64. But this transform in SimplifySetCC would sometimes undo it. Reviewed By: luismarques Differential Revision: https://reviews.llvm.org/D95289
2021-01-26 01:17:42 +01:00
; RV64IFD-NEXT: call func@plt
[RISCV] Implement RV64D codegen This patch: * Adds necessary RV64D codegen patterns * Modifies CC_RISCV so it will properly handle f64 types (with soft float ABI) Note that in general there is no reason to try to select fcvt.w[u].d rather than fcvt.l[u].d for i32 conversions because fptosi/fptoui produce poison if the input won't fit into the target type. Differential Revision: https://reviews.llvm.org/D53237 llvm-svn: 352833
2019-02-01 04:53:30 +01:00
; RV64IFD-NEXT: fmv.d.x ft0, a0
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-09 20:41:19 +01:00
; RV64IFD-NEXT: fld ft1, 0(sp) # 8-byte Folded Reload
[RISCV] Implement RV64D codegen This patch: * Adds necessary RV64D codegen patterns * Modifies CC_RISCV so it will properly handle f64 types (with soft float ABI) Note that in general there is no reason to try to select fcvt.w[u].d rather than fcvt.l[u].d for i32 conversions because fptosi/fptoui produce poison if the input won't fit into the target type. Differential Revision: https://reviews.llvm.org/D53237 llvm-svn: 352833
2019-02-01 04:53:30 +01:00
; RV64IFD-NEXT: fadd.d ft0, ft0, ft1
; RV64IFD-NEXT: .LBB0_2: # %return
; RV64IFD-NEXT: fmv.x.d a0, ft0
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-09 20:41:19 +01:00
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
[RISCV] Implement RV64D codegen This patch: * Adds necessary RV64D codegen patterns * Modifies CC_RISCV so it will properly handle f64 types (with soft float ABI) Note that in general there is no reason to try to select fcvt.w[u].d rather than fcvt.l[u].d for i32 conversions because fptosi/fptoui produce poison if the input won't fit into the target type. Differential Revision: https://reviews.llvm.org/D53237 llvm-svn: 352833
2019-02-01 04:53:30 +01:00
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
[RISCV] Add tests missed in r329871 llvm-svn: 329872
2018-04-12 07:36:44 +02:00
entry:
%cmp = icmp eq i32 %n, 0
br i1 %cmp, label %return, label %if.else
if.else:
%sub = add i32 %n, -1
%call = tail call double @func(double %d, i32 %sub)
%add = fadd double %call, %d
ret double %add
return:
ret double %d
}
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