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GlobalISel
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intrinsics
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rvv
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[RISCV] Use stack slot to handle SPLAT_VECTOR_PARTS on RV32.
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2021-04-26 15:43:02 -07:00 |
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add-before-shl.ll
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add-imm.ll
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[RISCV] Optimize addition with immediate
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2021-04-26 13:26:17 +08:00 |
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addc-adde-sube-subc.ll
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addcarry.ll
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addimm-mulimm.ll
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addrspacecast.ll
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align.ll
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alloca.ll
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alu8.ll
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alu16.ll
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[RISCV] Use SLLI/SRLI instead of SLLIW/SRLIW for (srl (and X, 0xffff), C) custom isel on RV64.
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2021-04-11 13:59:51 -07:00 |
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alu32.ll
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[RISCV] Teach targetShrinkDemandedConstant to preserve (and X, 0xffffffff).
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2021-03-25 09:03:25 -07:00 |
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alu64.ll
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analyze-branch.ll
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arith-with-overflow.ll
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atomic-cmpxchg-flag.ll
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atomic-cmpxchg.ll
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[RISCV] Copy isUnneededShiftMask from X86.
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2021-01-27 20:46:10 -08:00 |
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atomic-fence.ll
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atomic-load-store.ll
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atomic-rmw.ll
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[RISCV] Copy isUnneededShiftMask from X86.
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2021-01-27 20:46:10 -08:00 |
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attributes.ll
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[RISCV] Update the version number to v0.10 for vector.
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2021-01-30 07:20:05 +08:00 |
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blockaddress.ll
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branch-relaxation.ll
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branch.ll
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[RISCV] Add isel-patterns to optimize (a < 1) into blez (a <= 0)
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2021-03-15 11:32:43 -07:00 |
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bswap-ctlz-cttz-ctpop.ll
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[RISCV] Use SLLI/SRLI instead of SLLIW/SRLIW for (srl (and X, 0xffff), C) custom isel on RV64.
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2021-04-11 13:59:51 -07:00 |
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byval.ll
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callee-saved-fpr32s.ll
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callee-saved-fpr64s.ll
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callee-saved-gprs.ll
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calling-conv-half.ll
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[RISCV] Improve 64-bit integer constant materialization for more cases.
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2021-04-02 10:18:08 -07:00 |
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calling-conv-ilp32-ilp32f-common.ll
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calling-conv-ilp32-ilp32f-ilp32d-common.ll
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calling-conv-ilp32.ll
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calling-conv-ilp32d.ll
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calling-conv-ilp32f-ilp32d-common.ll
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calling-conv-lp64-lp64f-common.ll
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calling-conv-lp64-lp64f-lp64d-common.ll
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calling-conv-lp64.ll
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calling-conv-rv32f-ilp32.ll
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calling-conv-sext-zext.ll
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calls.ll
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cmp-bool.ll
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codemodel-lowering.ll
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compress-float.ll
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compress-inline-asm.ll
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compress.ll
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copy-frameindex.mir
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copysign-casts.ll
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[RISCV] Use softPromoteHalf legalization for fp16 without Zfh rather than PromoteFloat.
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2021-04-01 12:41:57 -07:00 |
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disable-tail-calls.ll
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disjoint.ll
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div.ll
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[RISCV] Use SLLI/SRLI instead of SLLIW/SRLIW for (srl (and X, 0xffff), C) custom isel on RV64.
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2021-04-11 13:59:51 -07:00 |
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double-arith.ll
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double-bitmanip-dagcombines.ll
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[RISCV] Improve 64-bit integer materialization for some cases.
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2021-04-01 09:12:52 -07:00 |
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double-br-fcmp.ll
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double-calling-conv.ll
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double-convert.ll
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[RISCV] Fix crash with fptosi.sat/fptoui.sat intrinsics on RV64. Add test cases.
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2021-04-22 15:18:15 -07:00 |
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double-fcmp.ll
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double-frem.ll
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double-imm.ll
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double-intrinsics.ll
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[RISCV] Improve 64-bit integer materialization for some cases.
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2021-04-01 09:12:52 -07:00 |
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double-isnan.ll
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double-mem.ll
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double-previous-failure.ll
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double-select-fcmp.ll
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double-stack-spill-restore.ll
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dwarf-eh.ll
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exception-pointer-register.ll
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fastcc-float.ll
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fastcc-int.ll
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fixups-diff.ll
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fixups-relax-diff.ll
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float-arith.ll
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float-bit-preserving-dagcombines.ll
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[RISCV] Improve 64-bit integer materialization for some cases.
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2021-04-01 09:12:52 -07:00 |
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float-bitmanip-dagcombines.ll
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float-br-fcmp.ll
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float-convert.ll
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[RISCV] Fix crash with fptosi.sat/fptoui.sat intrinsics on RV64. Add test cases.
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2021-04-22 15:18:15 -07:00 |
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float-fcmp.ll
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float-frem.ll
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float-imm.ll
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float-intrinsics.ll
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float-isnan.ll
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float-mem.ll
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float-select-fcmp.ll
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flt-rounds.ll
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fold-addi-loadstore.ll
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fp16-promote.ll
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[RISCV] Use softPromoteHalf legalization for fp16 without Zfh rather than PromoteFloat.
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2021-04-01 12:41:57 -07:00 |
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fp128.ll
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fp-imm.ll
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fpenv.ll
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[RISCV] Custom lowering of SET_ROUNDING
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2021-04-22 15:04:55 +07:00 |
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frame-info.ll
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frame.ll
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frameaddr-returnaddr.ll
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get-register-invalid.ll
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get-register-noreserve.ll
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get-register-reserve.ll
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get-setcc-result-type.ll
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ghccc-rv32.ll
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ghccc-rv64.ll
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half-arith.ll
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half-bitmanip-dagcombines.ll
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[RISCV] Use softPromoteHalf legalization for fp16 without Zfh rather than PromoteFloat.
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2021-04-01 12:41:57 -07:00 |
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half-br-fcmp.ll
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half-convert.ll
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[RISCV] Fix crash with fptosi.sat/fptoui.sat intrinsics on RV64. Add test cases.
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2021-04-22 15:18:15 -07:00 |
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half-fcmp.ll
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half-imm.ll
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half-intrinsics.ll
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half-isnan.ll
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half-mem.ll
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half-select-fcmp.ll
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hoist-global-addr-base.ll
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[RISCV] Add isel-patterns to optimize (a < 1) into blez (a <= 0)
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2021-03-15 11:32:43 -07:00 |
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i32-icmp.ll
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imm-cse.ll
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imm.ll
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[RISCV] Improve 64-bit integer constant materialization for more cases.
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2021-04-02 10:18:08 -07:00 |
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indirectbr.ll
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init-array.ll
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inline-asm-abi-names.ll
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inline-asm-clobbers.ll
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inline-asm-d-abi-names.ll
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inline-asm-d-constraint-f.ll
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inline-asm-f-abi-names.ll
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inline-asm-f-constraint-f.ll
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inline-asm-i-constraint-i1.ll
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inline-asm-invalid.ll
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inline-asm.ll
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interrupt-attr-args-error.ll
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interrupt-attr-callee.ll
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interrupt-attr-invalid.ll
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interrupt-attr-nocall.ll
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interrupt-attr-ret-error.ll
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interrupt-attr.ll
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jumptable.ll
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large-stack.ll
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[RISCV] remove redundant instruction when eliminate frame index
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2021-03-21 18:54:00 +08:00 |
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legalize-fneg.ll
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lit.local.cfg
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lsr-legaladdimm.ll
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machineoutliner.mir
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mattr-invalid-combination.ll
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mem64.ll
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mem.ll
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mir-target-flags.ll
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module-target-abi2.ll
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module-target-abi.ll
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mul.ll
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[RISCV] Add custom type legalization to form MULHSU when possible.
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2021-04-01 10:15:55 -07:00 |
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musttail-call.ll
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neg-abs.ll
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nomerge.ll
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option-nopic.ll
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option-norelax.ll
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option-norvc.ll
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option-pic.ll
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option-relax.ll
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option-rvc.ll
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out-of-reach-emergency-slot.mir
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patchable-function-entry.ll
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[RISCV] Support clang -fpatchable-function-entry && GNU function attribute 'patchable_function_entry'
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2021-03-16 10:02:35 -07:00 |
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pic-models.ll
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pr40333.ll
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prefetch.ll
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readcyclecounter.ll
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rem.ll
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[RISCV] Add i8/i16 test cases to div.ll and i8/i16/i64 to rem.ll. NFC
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2021-02-04 16:46:23 -08:00 |
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remat.ll
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reserved-reg-errors.ll
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reserved-regs.ll
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rotl-rotr.ll
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rv32e.ll
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rv32i-rv64i-float-double.ll
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rv32i-rv64i-half.ll
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[RISCV] Use softPromoteHalf legalization for fp16 without Zfh rather than PromoteFloat.
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2021-04-01 12:41:57 -07:00 |
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rv32zba.ll
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[RISCV] Rename Zb* extension tests to use lower case 'Z' in file names.
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2021-03-22 19:17:04 -07:00 |
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rv32zbb-intrinsic.ll
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Recommit "[RISCV] Add IR intrinsic for Zbb extension"
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2021-04-02 11:50:19 -07:00 |
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rv32zbb-zbp.ll
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[RISCV] Teach targetShrinkDemandedConstant to preserve (and X, 0xffff) when zext.h is supported.
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2021-04-11 10:03:35 -07:00 |
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rv32zbb.ll
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[RISCV] Rename Zb* extension tests to use lower case 'Z' in file names.
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2021-03-22 19:17:04 -07:00 |
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rv32zbc-intrinsic.ll
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[RISCV] Add IR intrinsics for Zbc extension
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2021-04-02 12:09:13 -07:00 |
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rv32zbe-intrinsic.ll
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[RISCV] [1/2] Add IR intrinsic for Zbe extension
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2021-04-25 19:14:34 -07:00 |
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rv32zbp-intrinsic.ll
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[RISCV] Teach DAG combine what bits Zbp instructions demanded from their inputs.
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2021-04-25 21:54:06 -07:00 |
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rv32zbp.ll
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[RISCV] Rename Zb* extension tests to use lower case 'Z' in file names.
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2021-03-22 19:17:04 -07:00 |
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rv32zbr.ll
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[RISCV] Add IR intrinsic for Zbr extension
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2021-04-02 10:58:45 -07:00 |
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rv32zbs.ll
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[RISCV] Rename Zb* extension tests to use lower case 'Z' in file names.
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2021-03-22 19:17:04 -07:00 |
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rv32zbt.ll
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[RISCV] Rename Zb* extension tests to use lower case 'Z' in file names.
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2021-03-22 19:17:04 -07:00 |
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rv64-large-stack.ll
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rv64d-double-convert.ll
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rv64f-float-convert.ll
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rv64f-half-convert.ll
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rv64i-complex-float.ll
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rv64i-demanded-bits.ll
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rv64i-double-softfloat.ll
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rv64i-exhaustive-w-insts.ll
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[RISCV] Optimize (and (shl GPR:, uimm5:), 0xffffffff) to use 2 shifts instead of 3.
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2021-03-25 23:31:01 -07:00 |
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rv64i-single-softfloat.ll
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rv64i-tricky-shifts.ll
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rv64i-w-insts-legalization.ll
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[RISCV] Add isel pattern to optimize (mul (and X, 0xffffffff), (and Y, 0xffffffff)) on RV64
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2021-03-20 14:55:46 -07:00 |
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rv64m-exhaustive-w-insts.ll
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[RISCV] Have sexti32 also recognize AssertZExt from types smaller than i32.
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2021-02-22 14:56:22 -08:00 |
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rv64m-w-insts-legalization.ll
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rv64zba.ll
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[RISCV] Teach targetShrinkDemandedConstant to preserve (and X, 0xffffffff).
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2021-03-25 09:03:25 -07:00 |
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rv64zbb-intrinsic.ll
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[RISCV] Use gorciw for i32 orc.b intrinsic when Zbp is enabled.
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2021-04-04 17:14:28 -07:00 |
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rv64zbb-zbp.ll
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[RISCV] Use SLLI/SRLI instead of SLLIW/SRLIW for (srl (and X, 0xffff), C) custom isel on RV64.
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2021-04-11 13:59:51 -07:00 |
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rv64zbb.ll
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[RISCV] Add RISCVISD opcodes for CLZW and CTZW.
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2021-03-31 09:40:07 -07:00 |
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rv64zbc-intrinsic.ll
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[RISCV] Add IR intrinsics for Zbc extension
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2021-04-02 12:09:13 -07:00 |
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rv64zbe-intrinsic.ll
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[RISCV] Teach DAG combine what bits Zbp instructions demanded from their inputs.
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2021-04-25 21:54:06 -07:00 |
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rv64zbp-intrinsic.ll
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[RISCV] Teach DAG combine what bits Zbp instructions demanded from their inputs.
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2021-04-25 21:54:06 -07:00 |
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rv64zbp.ll
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[RISCV] Improve 64-bit integer materialization for some cases.
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2021-04-01 09:12:52 -07:00 |
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rv64zbr.ll
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[RISCV] Add IR intrinsic for Zbr extension
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2021-04-02 10:58:45 -07:00 |
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rv64zbs.ll
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[RISCV] Improve 64-bit integer materialization for some cases.
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2021-04-01 09:12:52 -07:00 |
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rv64zbt.ll
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[RISCV] Rename Zb* extension tests to use lower case 'Z' in file names.
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2021-03-22 19:17:04 -07:00 |
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sadd_sat_plus.ll
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[RISCV] Add a special case to lowerSELECT for select of 2 constants with a SETLT condition.
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2021-04-07 13:47:17 -07:00 |
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sadd_sat.ll
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[RISCV] Add a special case to lowerSELECT for select of 2 constants with a SETLT condition.
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2021-04-07 13:47:17 -07:00 |
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saverestore.ll
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[RISCV] Don't emit save-restore call if function is a interrupt handler
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2021-04-16 12:54:47 +08:00 |
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scalable-vector-struct.ll
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[RISCV] Use whole register load/store for generic load/store.
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2021-02-09 15:52:04 +08:00 |
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sdata-limit-0.ll
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sdata-limit-4.ll
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sdata-limit-8.ll
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sdata-local-sym.ll
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select-and.ll
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select-bare.ll
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select-cc.ll
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[RISCV] Teach normaliseSetCC to canonicalize X > -1 to X >= 0 and X < 1 to 0 >= X.
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2021-03-12 11:50:10 -08:00 |
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select-const.ll
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select-optimize-multiple.ll
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select-optimize-multiple.mir
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select-or.ll
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setcc-logic.ll
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sext-zext-trunc.ll
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shadowcallstack.ll
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shift-masked-shamt.ll
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[RISCV] Copy isUnneededShiftMask from X86.
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2021-01-27 20:46:10 -08:00 |
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shifts.ll
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shrinkwrap.ll
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spill-fpr-scalar.ll
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[RISCV] Spilling for RISC-V V extension. (2nd version)
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2021-02-17 14:05:19 +08:00 |
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split-offsets.ll
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split-sp-adjust.ll
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srem-lkk.ll
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[TargetLowering][RISCV][AArch64][PowerPC] Enable BuildUDIV/BuildSDIV on illegal types before type legalization if we can find a larger legal type that supports MUL.
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2021-02-11 09:43:13 -08:00 |
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srem-seteq-illegal-types.ll
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[RISCV] Improve 64-bit integer materialization for some cases.
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2021-04-01 09:12:52 -07:00 |
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srem-vector-lkk.ll
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[RISCV] Improve 64-bit integer materialization for some cases.
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2021-04-01 09:12:52 -07:00 |
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ssub_sat_plus.ll
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[RISCV] Add a special case to lowerSELECT for select of 2 constants with a SETLT condition.
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2021-04-07 13:47:17 -07:00 |
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ssub_sat.ll
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[RISCV] Add a special case to lowerSELECT for select of 2 constants with a SETLT condition.
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2021-04-07 13:47:17 -07:00 |
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stack-realignment-with-variable-sized-objects.ll
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stack-realignment.ll
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[RISCV] remove redundant instruction when eliminate frame index
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2021-03-21 18:54:00 +08:00 |
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stack-slot-size.ll
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[RISCV][NFC] Add test of stack slot sizes of large split arguments
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2021-03-22 13:41:11 +00:00 |
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stack-store-check.ll
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subtarget-features-std-ext.ll
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tail-calls.ll
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target-abi-invalid.ll
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target-abi-valid.ll
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thread-pointer.ll
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tls-models.ll
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uadd_sat_plus.ll
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[RISCV] Improve i32 UADDSAT/USUBSAT on RV64.
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2021-03-16 07:44:06 -07:00 |
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uadd_sat.ll
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[RISCV] Improve i32 UADDSAT/USUBSAT on RV64.
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2021-03-16 07:44:06 -07:00 |
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umulo-128-legalisation-lowering.ll
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urem-lkk.ll
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[TargetLowering][RISCV][AArch64][PowerPC] Enable BuildUDIV/BuildSDIV on illegal types before type legalization if we can find a larger legal type that supports MUL.
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2021-02-11 09:43:13 -08:00 |
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urem-seteq-illegal-types.ll
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[RISCV] Improve 64-bit integer materialization for some cases.
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2021-04-01 09:12:52 -07:00 |
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urem-vector-lkk.ll
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usub_sat_plus.ll
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[RISCV] Improve i32 UADDSAT/USUBSAT on RV64.
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2021-03-16 07:44:06 -07:00 |
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usub_sat.ll
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[RISCV] Improve i32 UADDSAT/USUBSAT on RV64.
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2021-03-16 07:44:06 -07:00 |
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vararg.ll
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[RISCV] remove redundant instruction when eliminate frame index
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2021-03-21 18:54:00 +08:00 |
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vec3-setcc-crash.ll
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[RISCV] Fix a codegen crash in getSetCCResultType
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2021-01-27 10:22:54 +00:00 |
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vector-abi.ll
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[RISCV] Add a test showing incorrect codegen
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2021-04-05 11:51:03 +01:00 |
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verify-instr.mir
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wide-mem.ll
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xaluo.ll
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[RISCV] Add a pattern for (sext_inreg (mul (and X, 0xffffffff), (and Y, 0xffffffff)), i32) to suppress MULW formation
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2021-03-27 15:37:18 -07:00 |
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zext-with-load-is-free.ll
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zfh-imm.ll
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