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llvm-mirror/test/CodeGen
David Sherwood 1d6ba88234 [NFC][SVE] Add tests for inserting subvectors into illegal scalable vectors
A previous commit fixed some issues with inserting subvectors into
illegal scalable vectors:

0035decae7ab9ab1c988fdcede46598540afd1a0

I've created a patch that simply adds some of those same tests for SVE.

Differential Revision: https://reviews.llvm.org/D100641
2021-04-27 09:02:43 +01:00
..
AArch64 [NFC][SVE] Add tests for inserting subvectors into illegal scalable vectors 2021-04-27 09:02:43 +01:00
AMDGPU [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
ARC
ARM [ARM] Expand VMOVRRD simplification pattern 2021-04-26 12:27:38 +01:00
AVR
BPF BPF: generate BTF info for LD_imm64 loaded function pointer 2021-04-26 17:23:36 -07:00
Generic
Hexagon
Inputs
Lanai
M68k
Mips
MIR
MSP430
NVPTX [NVPTX] Enable lowering of atomics on local memory 2021-04-26 20:12:12 -04:00
PowerPC [XCOFF] make .file directive have directory info 2021-04-27 00:15:23 -04:00
RISCV [RISCV] Use stack slot to handle SPLAT_VECTOR_PARTS on RV32. 2021-04-26 15:43:02 -07:00
SPARC
SystemZ
Thumb
Thumb2 [ARM] Expand VMOVRRD simplification pattern 2021-04-26 12:27:38 +01:00
VE
WebAssembly
WinCFGuard
WinEH
X86 Reapply "[X86][AMX] Try to hoist AMX shapes' def" 2021-04-27 10:27:59 +08:00
XCore