2012-02-27 03:21:34 +01:00
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//===-- MipsRegisterInfo.td - Mips Register defs -----------*- tablegen -*-===//
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2007-06-06 09:42:06 +02:00
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 21:36:04 +01:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2007-06-06 09:42:06 +02:00
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//
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2011-04-15 23:51:11 +02:00
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//===----------------------------------------------------------------------===//
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2007-06-06 09:42:06 +02:00
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2011-04-15 23:51:11 +02:00
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//===----------------------------------------------------------------------===//
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2007-06-06 09:42:06 +02:00
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// Declarations that describe the MIPS register file
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2011-04-15 23:51:11 +02:00
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//===----------------------------------------------------------------------===//
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2011-09-22 19:57:32 +02:00
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let Namespace = "Mips" in {
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2013-06-01 01:45:26 +02:00
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def sub_32 : SubRegIndex<32>;
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2013-08-13 22:54:07 +02:00
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def sub_64 : SubRegIndex<64>;
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2013-06-01 01:45:26 +02:00
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def sub_lo : SubRegIndex<32>;
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def sub_hi : SubRegIndex<32, 32>;
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def sub_dsp16_19 : SubRegIndex<4, 16>;
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def sub_dsp20 : SubRegIndex<1, 20>;
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def sub_dsp21 : SubRegIndex<1, 21>;
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def sub_dsp22 : SubRegIndex<1, 22>;
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def sub_dsp23 : SubRegIndex<1, 23>;
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2011-09-22 19:57:32 +02:00
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}
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2007-06-06 09:42:06 +02:00
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2013-03-15 00:09:19 +01:00
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class Unallocatable {
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bit isAllocatable = 0;
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}
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2007-06-06 09:42:06 +02:00
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// We have banks of 32 registers each.
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2012-12-10 21:04:40 +01:00
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class MipsReg<bits<16> Enc, string n> : Register<n> {
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let HWEncoding = Enc;
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2007-06-06 09:42:06 +02:00
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let Namespace = "Mips";
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}
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2012-12-10 21:04:40 +01:00
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class MipsRegWithSubRegs<bits<16> Enc, string n, list<Register> subregs>
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2009-11-19 07:06:13 +01:00
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: RegisterWithSubRegs<n, subregs> {
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2012-12-10 21:04:40 +01:00
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let HWEncoding = Enc;
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2009-11-19 07:06:13 +01:00
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let Namespace = "Mips";
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}
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2007-06-06 09:42:06 +02:00
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// Mips CPU Registers
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2012-12-10 21:04:40 +01:00
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class MipsGPRReg<bits<16> Enc, string n> : MipsReg<Enc, n>;
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2007-06-06 09:42:06 +02:00
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2011-09-23 04:33:15 +02:00
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// Mips 64-bit CPU Registers
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2012-12-10 21:04:40 +01:00
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class Mips64GPRReg<bits<16> Enc, string n, list<Register> subregs>
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: MipsRegWithSubRegs<Enc, n, subregs> {
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2011-09-23 04:33:15 +02:00
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let SubRegIndices = [sub_32];
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}
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-05 21:05:21 +02:00
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// Mips 32-bit FPU Registers
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2012-12-10 21:04:40 +01:00
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class FPR<bits<16> Enc, string n> : MipsReg<Enc, n>;
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-05 21:05:21 +02:00
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// Mips 64-bit (aliased) FPU Registers
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2012-12-10 21:04:40 +01:00
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class AFPR<bits<16> Enc, string n, list<Register> subregs>
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: MipsRegWithSubRegs<Enc, n, subregs> {
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2013-08-21 00:58:56 +02:00
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let SubRegIndices = [sub_lo, sub_hi];
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2012-01-18 01:16:39 +01:00
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let CoveredBySubRegs = 1;
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-05 21:05:21 +02:00
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}
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2012-12-10 21:04:40 +01:00
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class AFPR64<bits<16> Enc, string n, list<Register> subregs>
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: MipsRegWithSubRegs<Enc, n, subregs> {
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2013-08-21 00:58:56 +02:00
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let SubRegIndices = [sub_lo, sub_hi];
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2013-08-28 02:34:17 +02:00
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let CoveredBySubRegs = 1;
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2011-09-22 05:48:47 +02:00
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}
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2013-08-13 22:54:07 +02:00
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// Mips 128-bit (aliased) MSA Registers
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class AFPR128<bits<16> Enc, string n, list<Register> subregs>
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: MipsRegWithSubRegs<Enc, n, subregs> {
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let SubRegIndices = [sub_64];
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}
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2013-03-29 04:27:21 +01:00
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// Accumulator Registers
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2013-08-08 23:54:26 +02:00
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class ACCReg<bits<16> Enc, string n, list<Register> subregs>
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2013-03-29 04:27:21 +01:00
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: MipsRegWithSubRegs<Enc, n, subregs> {
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let SubRegIndices = [sub_lo, sub_hi];
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let CoveredBySubRegs = 1;
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}
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2011-05-31 04:53:58 +02:00
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// Mips Hardware Registers
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2012-12-10 21:04:40 +01:00
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class HWR<bits<16> Enc, string n> : MipsReg<Enc, n>;
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2011-05-31 04:53:58 +02:00
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2011-04-15 23:51:11 +02:00
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//===----------------------------------------------------------------------===//
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-05 21:05:21 +02:00
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// Registers
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2011-04-15 23:51:11 +02:00
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//===----------------------------------------------------------------------===//
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-05 21:05:21 +02:00
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let Namespace = "Mips" in {
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// General Purpose Registers
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2012-07-11 22:51:50 +02:00
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def ZERO : MipsGPRReg< 0, "zero">, DwarfRegNum<[0]>;
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2012-11-02 22:26:03 +01:00
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def AT : MipsGPRReg< 1, "1">, DwarfRegNum<[1]>;
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-05 21:05:21 +02:00
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def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>;
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def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>;
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2011-05-26 21:25:47 +02:00
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def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[4]>;
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-05 21:05:21 +02:00
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def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>;
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def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>;
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def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>;
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def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<[8]>;
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def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<[9]>;
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def T2 : MipsGPRReg< 10, "10">, DwarfRegNum<[10]>;
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def T3 : MipsGPRReg< 11, "11">, DwarfRegNum<[11]>;
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def T4 : MipsGPRReg< 12, "12">, DwarfRegNum<[12]>;
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def T5 : MipsGPRReg< 13, "13">, DwarfRegNum<[13]>;
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def T6 : MipsGPRReg< 14, "14">, DwarfRegNum<[14]>;
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def T7 : MipsGPRReg< 15, "15">, DwarfRegNum<[15]>;
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def S0 : MipsGPRReg< 16, "16">, DwarfRegNum<[16]>;
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def S1 : MipsGPRReg< 17, "17">, DwarfRegNum<[17]>;
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def S2 : MipsGPRReg< 18, "18">, DwarfRegNum<[18]>;
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def S3 : MipsGPRReg< 19, "19">, DwarfRegNum<[19]>;
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def S4 : MipsGPRReg< 20, "20">, DwarfRegNum<[20]>;
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def S5 : MipsGPRReg< 21, "21">, DwarfRegNum<[21]>;
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def S6 : MipsGPRReg< 22, "22">, DwarfRegNum<[22]>;
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def S7 : MipsGPRReg< 23, "23">, DwarfRegNum<[23]>;
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def T8 : MipsGPRReg< 24, "24">, DwarfRegNum<[24]>;
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def T9 : MipsGPRReg< 25, "25">, DwarfRegNum<[25]>;
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def K0 : MipsGPRReg< 26, "26">, DwarfRegNum<[26]>;
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def K1 : MipsGPRReg< 27, "27">, DwarfRegNum<[27]>;
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2012-07-11 22:51:50 +02:00
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def GP : MipsGPRReg< 28, "gp">, DwarfRegNum<[28]>;
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def SP : MipsGPRReg< 29, "sp">, DwarfRegNum<[29]>;
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def FP : MipsGPRReg< 30, "fp">, DwarfRegNum<[30]>;
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def RA : MipsGPRReg< 31, "ra">, DwarfRegNum<[31]>;
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2011-03-04 18:51:39 +01:00
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2011-09-23 04:33:15 +02:00
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// General Purpose 64-bit Registers
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2012-07-11 22:51:50 +02:00
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def ZERO_64 : Mips64GPRReg< 0, "zero", [ZERO]>, DwarfRegNum<[0]>;
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2012-11-02 22:26:03 +01:00
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def AT_64 : Mips64GPRReg< 1, "1", [AT]>, DwarfRegNum<[1]>;
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2012-02-02 03:56:14 +01:00
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def V0_64 : Mips64GPRReg< 2, "2", [V0]>, DwarfRegNum<[2]>;
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def V1_64 : Mips64GPRReg< 3, "3", [V1]>, DwarfRegNum<[3]>;
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def A0_64 : Mips64GPRReg< 4, "4", [A0]>, DwarfRegNum<[4]>;
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def A1_64 : Mips64GPRReg< 5, "5", [A1]>, DwarfRegNum<[5]>;
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def A2_64 : Mips64GPRReg< 6, "6", [A2]>, DwarfRegNum<[6]>;
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def A3_64 : Mips64GPRReg< 7, "7", [A3]>, DwarfRegNum<[7]>;
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def T0_64 : Mips64GPRReg< 8, "8", [T0]>, DwarfRegNum<[8]>;
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def T1_64 : Mips64GPRReg< 9, "9", [T1]>, DwarfRegNum<[9]>;
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2012-02-27 03:21:34 +01:00
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def T2_64 : Mips64GPRReg< 10, "10", [T2]>, DwarfRegNum<[10]>;
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def T3_64 : Mips64GPRReg< 11, "11", [T3]>, DwarfRegNum<[11]>;
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def T4_64 : Mips64GPRReg< 12, "12", [T4]>, DwarfRegNum<[12]>;
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def T5_64 : Mips64GPRReg< 13, "13", [T5]>, DwarfRegNum<[13]>;
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def T6_64 : Mips64GPRReg< 14, "14", [T6]>, DwarfRegNum<[14]>;
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def T7_64 : Mips64GPRReg< 15, "15", [T7]>, DwarfRegNum<[15]>;
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def S0_64 : Mips64GPRReg< 16, "16", [S0]>, DwarfRegNum<[16]>;
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def S1_64 : Mips64GPRReg< 17, "17", [S1]>, DwarfRegNum<[17]>;
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def S2_64 : Mips64GPRReg< 18, "18", [S2]>, DwarfRegNum<[18]>;
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def S3_64 : Mips64GPRReg< 19, "19", [S3]>, DwarfRegNum<[19]>;
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def S4_64 : Mips64GPRReg< 20, "20", [S4]>, DwarfRegNum<[20]>;
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def S5_64 : Mips64GPRReg< 21, "21", [S5]>, DwarfRegNum<[21]>;
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def S6_64 : Mips64GPRReg< 22, "22", [S6]>, DwarfRegNum<[22]>;
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2012-02-02 03:56:14 +01:00
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def S7_64 : Mips64GPRReg< 23, "23", [S7]>, DwarfRegNum<[23]>;
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|
|
def T8_64 : Mips64GPRReg< 24, "24", [T8]>, DwarfRegNum<[24]>;
|
|
|
|
def T9_64 : Mips64GPRReg< 25, "25", [T9]>, DwarfRegNum<[25]>;
|
|
|
|
def K0_64 : Mips64GPRReg< 26, "26", [K0]>, DwarfRegNum<[26]>;
|
|
|
|
def K1_64 : Mips64GPRReg< 27, "27", [K1]>, DwarfRegNum<[27]>;
|
2012-07-11 22:51:50 +02:00
|
|
|
def GP_64 : Mips64GPRReg< 28, "gp", [GP]>, DwarfRegNum<[28]>;
|
|
|
|
def SP_64 : Mips64GPRReg< 29, "sp", [SP]>, DwarfRegNum<[29]>;
|
|
|
|
def FP_64 : Mips64GPRReg< 30, "fp", [FP]>, DwarfRegNum<[30]>;
|
|
|
|
def RA_64 : Mips64GPRReg< 31, "ra", [RA]>, DwarfRegNum<[31]>;
|
2011-09-23 04:33:15 +02:00
|
|
|
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-05 21:05:21 +02:00
|
|
|
/// Mips Single point precision FPU Registers
|
2013-07-17 21:09:27 +02:00
|
|
|
foreach I = 0-31 in
|
|
|
|
def F#I : FPR<I, "f"#I>, DwarfRegNum<[!add(I, 32)]>;
|
2011-03-04 18:51:39 +01:00
|
|
|
|
2013-08-21 00:58:56 +02:00
|
|
|
// Higher half of 64-bit FP registers.
|
|
|
|
foreach I = 0-31 in
|
|
|
|
def F_HI#I : FPR<I, "f"#I>, DwarfRegNum<[!add(I, 32)]>;
|
|
|
|
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-05 21:05:21 +02:00
|
|
|
/// Mips Double point precision FPU Registers (aliased
|
|
|
|
/// with the single precision to hold 64 bit values)
|
2013-07-17 21:09:27 +02:00
|
|
|
foreach I = 0-15 in
|
|
|
|
def D#I : AFPR<!shl(I, 1), "f"#!shl(I, 1),
|
|
|
|
[!cast<FPR>("F"#!shl(I, 1)),
|
|
|
|
!cast<FPR>("F"#!add(!shl(I, 1), 1))]>;
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-05 21:05:21 +02:00
|
|
|
|
2011-09-22 05:48:47 +02:00
|
|
|
/// Mips Double point precision FPU Registers in MFP64 mode.
|
2013-07-17 21:09:27 +02:00
|
|
|
foreach I = 0-31 in
|
2013-08-21 00:58:56 +02:00
|
|
|
def D#I#_64 : AFPR64<I, "f"#I, [!cast<FPR>("F"#I), !cast<FPR>("F_HI"#I)]>,
|
2013-07-17 21:09:27 +02:00
|
|
|
DwarfRegNum<[!add(I, 32)]>;
|
2011-09-22 05:48:47 +02:00
|
|
|
|
2013-08-13 22:54:07 +02:00
|
|
|
/// Mips MSA registers
|
|
|
|
/// MSA and FPU cannot both be present unless the FPU has 64-bit registers
|
2013-08-21 10:48:25 +02:00
|
|
|
foreach I = 0-31 in
|
2013-08-21 11:09:52 +02:00
|
|
|
def W#I : AFPR128<I, "w"#I, [!cast<AFPR64>("D"#I#"_64")]>,
|
2013-08-21 10:48:25 +02:00
|
|
|
DwarfRegNum<[!add(I, 32)]>;
|
2013-08-13 22:54:07 +02:00
|
|
|
|
2008-08-02 21:42:36 +02:00
|
|
|
// Hi/Lo registers
|
2013-10-15 03:00:00 +02:00
|
|
|
def HI0 : MipsReg<0, "ac0">, DwarfRegNum<[64]>;
|
|
|
|
def HI1 : MipsReg<1, "ac1">, DwarfRegNum<[176]>;
|
|
|
|
def HI2 : MipsReg<2, "ac2">, DwarfRegNum<[178]>;
|
|
|
|
def HI3 : MipsReg<3, "ac3">, DwarfRegNum<[180]>;
|
|
|
|
def LO0 : MipsReg<0, "ac0">, DwarfRegNum<[65]>;
|
|
|
|
def LO1 : MipsReg<1, "ac1">, DwarfRegNum<[177]>;
|
|
|
|
def LO2 : MipsReg<2, "ac2">, DwarfRegNum<[179]>;
|
|
|
|
def LO3 : MipsReg<3, "ac3">, DwarfRegNum<[181]>;
|
2008-08-02 21:42:36 +02:00
|
|
|
|
2011-09-23 20:11:56 +02:00
|
|
|
let SubRegIndices = [sub_32] in {
|
2013-08-14 02:47:08 +02:00
|
|
|
def HI0_64 : RegisterWithSubRegs<"hi", [HI0]>;
|
|
|
|
def LO0_64 : RegisterWithSubRegs<"lo", [LO0]>;
|
2011-09-23 20:11:56 +02:00
|
|
|
}
|
|
|
|
|
2013-07-01 22:31:44 +02:00
|
|
|
// FP control registers.
|
|
|
|
foreach I = 0-31 in
|
|
|
|
def FCR#I : MipsReg<#I, ""#I>;
|
2011-05-31 04:53:58 +02:00
|
|
|
|
2013-07-26 21:03:48 +02:00
|
|
|
// FP condition code registers.
|
|
|
|
foreach I = 0-7 in
|
|
|
|
def FCC#I : MipsReg<#I, "fcc"#I>;
|
2012-07-11 22:51:50 +02:00
|
|
|
|
2013-09-16 12:29:42 +02:00
|
|
|
// COP2 registers.
|
|
|
|
foreach I = 0-31 in
|
|
|
|
def COP2#I : MipsReg<#I, ""#I>;
|
|
|
|
|
2014-05-08 15:02:11 +02:00
|
|
|
// COP3 registers.
|
|
|
|
foreach I = 0-31 in
|
|
|
|
def COP3#I : MipsReg<#I, ""#I>;
|
|
|
|
|
2012-08-17 22:16:42 +02:00
|
|
|
// PC register
|
|
|
|
def PC : Register<"pc">;
|
|
|
|
|
2014-11-11 11:31:31 +01:00
|
|
|
// Hardware registers
|
|
|
|
def HWR0 : MipsReg<0, "hwr_cpunum">;
|
|
|
|
def HWR1 : MipsReg<1, "hwr_synci_step">;
|
|
|
|
def HWR2 : MipsReg<2, "hwr_cc">;
|
|
|
|
def HWR3 : MipsReg<3, "hwr_ccres">;
|
|
|
|
|
|
|
|
foreach I = 4-31 in
|
[mips] Rewrite MipsAsmParser and MipsOperand.
Summary:
Highlights:
- Registers are resolved much later (by the render method).
Prior to that point, GPR32's/GPR64's are GPR's regardless of register
size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register
size or FR mode. Numeric registers can be anything.
- All registers are parsed the same way everywhere (even when handling
symbol aliasing)
- One consequence is that all registers can be specified numerically
almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing
but that can be easily resolved.
- Removes the need for the hasConsumedDollar hack
- Parenthesis and Bracket suffixes are handled generically
- Micromips instructions are parsed directly instead of going through the
standard encodings first.
- rdhwr accepts all 32 registers, and the following instructions that previously
xfailed now work:
ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d,
c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1
- Diagnostics involving registers point at the correct character (the $)
- There's only one kind of immediate in MipsOperand. LSA immediates are handled
by the predicate and renderer.
Lowlights:
- Hardcoded '$zero' in the div patterns is handled with a hack.
MipsOperand::isReg() will return true for a k_RegisterIndex token
with Index == 0 and getReg() will return ZERO for this case. Note that it
doesn't return ZERO_64 on isGP64() targets.
- I haven't cleaned up all of the now-unused functions.
Some more of the generic parser could be removed too (integers and relocs
for example).
- insve.df needed a custom decoder to handle the implicit fourth operand that
was needed to make it parse correctly. The difficulty was that the matcher
expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this.
Reviewers: matheusalmeida, vmedic
Reviewed By: matheusalmeida
Differential Revision: http://llvm-reviews.chandlerc.com/D3222
llvm-svn: 205292
2014-04-01 12:35:28 +02:00
|
|
|
def HWR#I : MipsReg<#I, ""#I>;
|
2012-09-22 01:48:37 +02:00
|
|
|
|
|
|
|
// Accum registers
|
2013-08-14 02:47:08 +02:00
|
|
|
foreach I = 0-3 in
|
|
|
|
def AC#I : ACCReg<#I, "ac"#I,
|
|
|
|
[!cast<Register>("LO"#I), !cast<Register>("HI"#I)]>;
|
2013-03-29 04:27:21 +01:00
|
|
|
|
2013-08-14 02:47:08 +02:00
|
|
|
def AC0_64 : ACCReg<0, "ac0", [LO0_64, HI0_64]>;
|
2012-09-22 01:48:37 +02:00
|
|
|
|
2013-05-03 20:37:49 +02:00
|
|
|
// DSP-ASE control register fields.
|
|
|
|
def DSPPos : Register<"">;
|
|
|
|
def DSPSCount : Register<"">;
|
|
|
|
def DSPCarry : Register<"">;
|
|
|
|
def DSPEFI : Register<"">;
|
|
|
|
def DSPOutFlag16_19 : Register<"">;
|
|
|
|
def DSPOutFlag20 : Register<"">;
|
|
|
|
def DSPOutFlag21 : Register<"">;
|
|
|
|
def DSPOutFlag22 : Register<"">;
|
|
|
|
def DSPOutFlag23 : Register<"">;
|
2013-05-01 00:37:26 +02:00
|
|
|
def DSPCCond : Register<"">;
|
2013-05-03 20:37:49 +02:00
|
|
|
|
|
|
|
let SubRegIndices = [sub_dsp16_19, sub_dsp20, sub_dsp21, sub_dsp22,
|
|
|
|
sub_dsp23] in
|
|
|
|
def DSPOutFlag : RegisterWithSubRegs<"", [DSPOutFlag16_19, DSPOutFlag20,
|
|
|
|
DSPOutFlag21, DSPOutFlag22,
|
|
|
|
DSPOutFlag23]>;
|
2013-08-28 12:26:24 +02:00
|
|
|
|
|
|
|
// MSA-ASE control registers.
|
2013-10-21 14:26:50 +02:00
|
|
|
def MSAIR : MipsReg<0, "0">;
|
|
|
|
def MSACSR : MipsReg<1, "1">;
|
|
|
|
def MSAAccess : MipsReg<2, "2">;
|
|
|
|
def MSASave : MipsReg<3, "3">;
|
|
|
|
def MSAModify : MipsReg<4, "4">;
|
|
|
|
def MSARequest : MipsReg<5, "5">;
|
|
|
|
def MSAMap : MipsReg<6, "6">;
|
|
|
|
def MSAUnmap : MipsReg<7, "7">;
|
2014-03-20 12:51:58 +01:00
|
|
|
|
|
|
|
// Octeon multiplier and product registers
|
|
|
|
def MPL0 : MipsReg<0, "mpl0">;
|
|
|
|
def MPL1 : MipsReg<1, "mpl1">;
|
|
|
|
def MPL2 : MipsReg<2, "mpl2">;
|
|
|
|
def P0 : MipsReg<0, "p0">;
|
|
|
|
def P1 : MipsReg<1, "p1">;
|
|
|
|
def P2 : MipsReg<2, "p2">;
|
|
|
|
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-05 21:05:21 +02:00
|
|
|
}
|
|
|
|
|
2011-04-15 23:51:11 +02:00
|
|
|
//===----------------------------------------------------------------------===//
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-05 21:05:21 +02:00
|
|
|
// Register Classes
|
2011-04-15 23:51:11 +02:00
|
|
|
//===----------------------------------------------------------------------===//
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-05 21:05:21 +02:00
|
|
|
|
2013-08-07 01:08:38 +02:00
|
|
|
class GPR32Class<list<ValueType> regTypes> :
|
2012-09-22 01:48:37 +02:00
|
|
|
RegisterClass<"Mips", regTypes, 32, (add
|
2012-07-11 22:51:50 +02:00
|
|
|
// Reserved
|
|
|
|
ZERO, AT,
|
2007-06-06 09:42:06 +02:00
|
|
|
// Return Values and Arguments
|
2011-06-16 01:28:14 +02:00
|
|
|
V0, V1, A0, A1, A2, A3,
|
2007-06-06 09:42:06 +02:00
|
|
|
// Not preserved across procedure calls
|
2012-07-11 22:51:50 +02:00
|
|
|
T0, T1, T2, T3, T4, T5, T6, T7,
|
2007-06-06 09:42:06 +02:00
|
|
|
// Callee save
|
|
|
|
S0, S1, S2, S3, S4, S5, S6, S7,
|
2012-07-11 22:51:50 +02:00
|
|
|
// Not preserved across procedure calls
|
|
|
|
T8, T9,
|
2007-06-06 09:42:06 +02:00
|
|
|
// Reserved
|
2012-07-11 22:51:50 +02:00
|
|
|
K0, K1, GP, SP, FP, RA)>;
|
2008-06-07 23:32:41 +02:00
|
|
|
|
2013-08-07 01:08:38 +02:00
|
|
|
def GPR32 : GPR32Class<[i32]>;
|
2013-08-14 02:53:38 +02:00
|
|
|
def DSPR : GPR32Class<[v4i8, v2i16]>;
|
2012-09-22 01:48:37 +02:00
|
|
|
|
2014-10-21 10:23:11 +02:00
|
|
|
def GPRMM16 : RegisterClass<"Mips", [i32], 32, (add
|
|
|
|
// Callee save
|
2014-11-24 14:29:59 +01:00
|
|
|
S0, S1,
|
|
|
|
// Return Values and Arguments
|
|
|
|
V0, V1, A0, A1, A2, A3)>;
|
2014-10-21 10:23:11 +02:00
|
|
|
|
2014-11-24 15:25:53 +01:00
|
|
|
def GPRMM16Zero : RegisterClass<"Mips", [i32], 32, (add
|
|
|
|
// Reserved
|
|
|
|
ZERO,
|
|
|
|
// Callee save
|
2014-11-26 19:56:38 +01:00
|
|
|
S1,
|
|
|
|
// Return Values and Arguments
|
|
|
|
V0, V1, A0, A1, A2, A3)>;
|
2014-11-24 15:25:53 +01:00
|
|
|
|
2015-02-10 17:36:20 +01:00
|
|
|
def GPRMM16MoveP : RegisterClass<"Mips", [i32], 32, (add
|
|
|
|
// Reserved
|
|
|
|
ZERO,
|
|
|
|
// Callee save
|
|
|
|
S1,
|
|
|
|
// Return Values and Arguments
|
|
|
|
V0, V1,
|
|
|
|
// Callee save
|
|
|
|
S0, S2, S3, S4)>;
|
|
|
|
|
2013-08-07 01:08:38 +02:00
|
|
|
def GPR64 : RegisterClass<"Mips", [i64], 64, (add
|
2012-07-11 22:51:50 +02:00
|
|
|
// Reserved
|
|
|
|
ZERO_64, AT_64,
|
2011-09-23 20:11:56 +02:00
|
|
|
// Return Values and Arguments
|
|
|
|
V0_64, V1_64, A0_64, A1_64, A2_64, A3_64,
|
|
|
|
// Not preserved across procedure calls
|
2012-07-11 22:51:50 +02:00
|
|
|
T0_64, T1_64, T2_64, T3_64, T4_64, T5_64, T6_64, T7_64,
|
2011-09-23 20:11:56 +02:00
|
|
|
// Callee save
|
|
|
|
S0_64, S1_64, S2_64, S3_64, S4_64, S5_64, S6_64, S7_64,
|
2012-07-11 22:51:50 +02:00
|
|
|
// Not preserved across procedure calls
|
|
|
|
T8_64, T9_64,
|
2011-09-23 20:11:56 +02:00
|
|
|
// Reserved
|
2012-07-11 22:51:50 +02:00
|
|
|
K0_64, K1_64, GP_64, SP_64, FP_64, RA_64)>;
|
2011-09-23 20:11:56 +02:00
|
|
|
|
2012-05-17 00:19:56 +02:00
|
|
|
def CPU16Regs : RegisterClass<"Mips", [i32], 32, (add
|
|
|
|
// Return Values and Arguments
|
|
|
|
V0, V1, A0, A1, A2, A3,
|
|
|
|
// Callee save
|
|
|
|
S0, S1)>;
|
|
|
|
|
2013-08-04 03:13:25 +02:00
|
|
|
def CPU16RegsPlusSP : RegisterClass<"Mips", [i32], 32, (add
|
|
|
|
// Return Values and Arguments
|
|
|
|
V0, V1, A0, A1, A2, A3,
|
|
|
|
// Callee save
|
|
|
|
S0, S1,
|
|
|
|
SP)>;
|
|
|
|
|
2013-03-15 00:09:19 +01:00
|
|
|
def CPURAReg : RegisterClass<"Mips", [i32], 32, (add RA)>, Unallocatable;
|
2012-05-24 20:32:33 +02:00
|
|
|
|
2013-03-15 00:09:19 +01:00
|
|
|
def CPUSPReg : RegisterClass<"Mips", [i32], 32, (add SP)>, Unallocatable;
|
2012-05-17 00:19:56 +02:00
|
|
|
|
2009-03-21 01:05:07 +01:00
|
|
|
// 64bit fp:
|
|
|
|
// * FGR64 - 32 64-bit registers
|
2011-03-04 18:51:39 +01:00
|
|
|
// * AFGR64 - 16 32-bit even registers (32-bit FP Mode)
|
2009-03-21 01:05:07 +01:00
|
|
|
//
|
|
|
|
// 32bit fp:
|
|
|
|
// * FGR32 - 16 32-bit even registers
|
|
|
|
// * FGR32 - 32 32-bit registers (single float only mode)
|
2011-06-16 01:28:14 +02:00
|
|
|
def FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)>;
|
2008-06-07 23:32:41 +02:00
|
|
|
|
2013-08-28 02:34:17 +02:00
|
|
|
def FGRH32 : RegisterClass<"Mips", [f32], 32, (sequence "F_HI%u", 0, 31)>,
|
|
|
|
Unallocatable;
|
2013-08-21 00:58:56 +02:00
|
|
|
|
2011-06-16 01:28:14 +02:00
|
|
|
def AFGR64 : RegisterClass<"Mips", [f64], 64, (add
|
2008-06-07 23:32:41 +02:00
|
|
|
// Return Values and Arguments
|
2012-07-11 22:51:50 +02:00
|
|
|
D0, D1,
|
|
|
|
// Not preserved across procedure calls
|
|
|
|
D2, D3, D4, D5,
|
|
|
|
// Return Values and Arguments
|
|
|
|
D6, D7,
|
2008-06-07 23:32:41 +02:00
|
|
|
// Not preserved across procedure calls
|
2012-07-11 22:51:50 +02:00
|
|
|
D8, D9,
|
2008-06-07 23:32:41 +02:00
|
|
|
// Callee save
|
2012-05-04 05:30:34 +02:00
|
|
|
D10, D11, D12, D13, D14, D15)>;
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-05 21:05:21 +02:00
|
|
|
|
2012-05-04 05:30:34 +02:00
|
|
|
def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)>;
|
2011-09-23 20:11:56 +02:00
|
|
|
|
2014-07-10 15:38:23 +02:00
|
|
|
// Used to reserve odd registers when given -mattr=+nooddspreg
|
2014-07-16 17:34:07 +02:00
|
|
|
// FIXME: Remove double precision registers from this set.
|
2014-07-10 15:38:23 +02:00
|
|
|
def OddSP : RegisterClass<"Mips", [f32], 32,
|
|
|
|
(add (decimate (sequence "F%u", 1, 31), 2),
|
2014-07-16 17:34:07 +02:00
|
|
|
(decimate (sequence "F_HI%u", 1, 31), 2),
|
|
|
|
(decimate (sequence "D%u", 1, 15), 2),
|
|
|
|
(decimate (sequence "D%u_64", 1, 31), 2))>,
|
2014-07-10 15:38:23 +02:00
|
|
|
Unallocatable;
|
|
|
|
|
2013-07-01 22:31:44 +02:00
|
|
|
// FP control registers.
|
|
|
|
def CCR : RegisterClass<"Mips", [i32], 32, (sequence "FCR%u", 0, 31)>,
|
|
|
|
Unallocatable;
|
|
|
|
|
|
|
|
// FP condition code registers.
|
2013-07-26 21:03:48 +02:00
|
|
|
def FCC : RegisterClass<"Mips", [i32], 32, (sequence "FCC%u", 0, 7)>,
|
|
|
|
Unallocatable;
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-05 21:05:21 +02:00
|
|
|
|
2014-06-12 15:39:06 +02:00
|
|
|
// MIPS32r6/MIPS64r6 store FPU condition codes in normal FGR registers.
|
|
|
|
// This class allows us to represent this in codegen patterns.
|
|
|
|
def FGRCC : RegisterClass<"Mips", [i32], 32, (sequence "F%u", 0, 31)>;
|
|
|
|
|
2013-08-23 12:10:13 +02:00
|
|
|
def MSA128B: RegisterClass<"Mips", [v16i8], 128,
|
|
|
|
(sequence "W%u", 0, 31)>;
|
|
|
|
def MSA128H: RegisterClass<"Mips", [v8i16, v8f16], 128,
|
|
|
|
(sequence "W%u", 0, 31)>;
|
|
|
|
def MSA128W: RegisterClass<"Mips", [v4i32, v4f32], 128,
|
|
|
|
(sequence "W%u", 0, 31)>;
|
|
|
|
def MSA128D: RegisterClass<"Mips", [v2i64, v2f64], 128,
|
|
|
|
(sequence "W%u", 0, 31)>;
|
2015-02-23 18:22:16 +01:00
|
|
|
def MSA128WEvens: RegisterClass<"Mips", [v4i32, v4f32], 128,
|
|
|
|
(decimate (sequence "W%u", 0, 31), 2)>;
|
2013-08-13 22:54:07 +02:00
|
|
|
|
2013-08-28 12:26:24 +02:00
|
|
|
def MSACtrl: RegisterClass<"Mips", [i32], 32, (add
|
|
|
|
MSAIR, MSACSR, MSAAccess, MSASave, MSAModify, MSARequest, MSAMap, MSAUnmap)>;
|
|
|
|
|
2009-05-27 19:23:44 +02:00
|
|
|
// Hi/Lo Registers
|
2013-08-14 02:47:08 +02:00
|
|
|
def LO32 : RegisterClass<"Mips", [i32], 32, (add LO0)>;
|
|
|
|
def HI32 : RegisterClass<"Mips", [i32], 32, (add HI0)>;
|
|
|
|
def LO32DSP : RegisterClass<"Mips", [i32], 32, (sequence "LO%u", 0, 3)>;
|
|
|
|
def HI32DSP : RegisterClass<"Mips", [i32], 32, (sequence "HI%u", 0, 3)>;
|
|
|
|
def LO64 : RegisterClass<"Mips", [i64], 64, (add LO0_64)>;
|
|
|
|
def HI64 : RegisterClass<"Mips", [i64], 64, (add HI0_64)>;
|
2008-08-02 21:42:36 +02:00
|
|
|
|
2011-05-31 04:53:58 +02:00
|
|
|
// Hardware registers
|
[mips] Rewrite MipsAsmParser and MipsOperand.
Summary:
Highlights:
- Registers are resolved much later (by the render method).
Prior to that point, GPR32's/GPR64's are GPR's regardless of register
size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register
size or FR mode. Numeric registers can be anything.
- All registers are parsed the same way everywhere (even when handling
symbol aliasing)
- One consequence is that all registers can be specified numerically
almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing
but that can be easily resolved.
- Removes the need for the hasConsumedDollar hack
- Parenthesis and Bracket suffixes are handled generically
- Micromips instructions are parsed directly instead of going through the
standard encodings first.
- rdhwr accepts all 32 registers, and the following instructions that previously
xfailed now work:
ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d,
c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1
- Diagnostics involving registers point at the correct character (the $)
- There's only one kind of immediate in MipsOperand. LSA immediates are handled
by the predicate and renderer.
Lowlights:
- Hardcoded '$zero' in the div patterns is handled with a hack.
MipsOperand::isReg() will return true for a k_RegisterIndex token
with Index == 0 and getReg() will return ZERO for this case. Note that it
doesn't return ZERO_64 on isGP64() targets.
- I haven't cleaned up all of the now-unused functions.
Some more of the generic parser could be removed too (integers and relocs
for example).
- insve.df needed a custom decoder to handle the implicit fourth operand that
was needed to make it parse correctly. The difficulty was that the matcher
expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this.
Reviewers: matheusalmeida, vmedic
Reviewed By: matheusalmeida
Differential Revision: http://llvm-reviews.chandlerc.com/D3222
llvm-svn: 205292
2014-04-01 12:35:28 +02:00
|
|
|
def HWRegs : RegisterClass<"Mips", [i32], 32, (sequence "HWR%u", 0, 31)>,
|
|
|
|
Unallocatable;
|
2011-12-08 00:26:03 +01:00
|
|
|
|
2012-09-26 21:25:21 +02:00
|
|
|
// Accumulator Registers
|
2013-08-08 23:54:26 +02:00
|
|
|
def ACC64 : RegisterClass<"Mips", [untyped], 64, (add AC0)> {
|
2013-03-29 04:27:21 +01:00
|
|
|
let Size = 64;
|
|
|
|
}
|
|
|
|
|
2013-08-08 23:54:26 +02:00
|
|
|
def ACC128 : RegisterClass<"Mips", [untyped], 128, (add AC0_64)> {
|
2013-03-29 04:27:21 +01:00
|
|
|
let Size = 128;
|
|
|
|
}
|
|
|
|
|
2013-08-08 23:54:26 +02:00
|
|
|
def ACC64DSP : RegisterClass<"Mips", [untyped], 64, (sequence "AC%u", 0, 3)> {
|
2013-03-29 04:27:21 +01:00
|
|
|
let Size = 64;
|
|
|
|
}
|
2013-01-12 02:03:14 +01:00
|
|
|
|
2013-05-01 00:37:26 +02:00
|
|
|
def DSPCC : RegisterClass<"Mips", [v4i8, v2i16], 32, (add DSPCCond)>;
|
|
|
|
|
2013-09-16 12:29:42 +02:00
|
|
|
// Coprocessor 2 registers.
|
|
|
|
def COP2 : RegisterClass<"Mips", [i32], 32, (sequence "COP2%u", 0, 31)>,
|
|
|
|
Unallocatable;
|
|
|
|
|
2014-05-08 15:02:11 +02:00
|
|
|
// Coprocessor 3 registers.
|
|
|
|
def COP3 : RegisterClass<"Mips", [i32], 32, (sequence "COP3%u", 0, 31)>,
|
|
|
|
Unallocatable;
|
|
|
|
|
2014-03-20 12:51:58 +01:00
|
|
|
// Octeon multiplier and product registers
|
|
|
|
def OCTEON_MPL : RegisterClass<"Mips", [i64], 64, (add MPL0, MPL1, MPL2)>,
|
|
|
|
Unallocatable;
|
|
|
|
def OCTEON_P : RegisterClass<"Mips", [i64], 64, (add P0, P1, P2)>,
|
|
|
|
Unallocatable;
|
|
|
|
|
2013-05-01 00:37:26 +02:00
|
|
|
// Register Operands.
|
2013-06-19 12:14:36 +02:00
|
|
|
|
|
|
|
class MipsAsmRegOperand : AsmOperandClass {
|
2014-09-04 15:23:44 +02:00
|
|
|
let ParserMethod = "parseAnyRegister";
|
2013-01-12 02:03:14 +01:00
|
|
|
}
|
|
|
|
|
2014-03-31 20:51:43 +02:00
|
|
|
def GPR64AsmOperand : MipsAsmRegOperand {
|
[mips] Rewrite MipsAsmParser and MipsOperand.
Summary:
Highlights:
- Registers are resolved much later (by the render method).
Prior to that point, GPR32's/GPR64's are GPR's regardless of register
size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register
size or FR mode. Numeric registers can be anything.
- All registers are parsed the same way everywhere (even when handling
symbol aliasing)
- One consequence is that all registers can be specified numerically
almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing
but that can be easily resolved.
- Removes the need for the hasConsumedDollar hack
- Parenthesis and Bracket suffixes are handled generically
- Micromips instructions are parsed directly instead of going through the
standard encodings first.
- rdhwr accepts all 32 registers, and the following instructions that previously
xfailed now work:
ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d,
c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1
- Diagnostics involving registers point at the correct character (the $)
- There's only one kind of immediate in MipsOperand. LSA immediates are handled
by the predicate and renderer.
Lowlights:
- Hardcoded '$zero' in the div patterns is handled with a hack.
MipsOperand::isReg() will return true for a k_RegisterIndex token
with Index == 0 and getReg() will return ZERO for this case. Note that it
doesn't return ZERO_64 on isGP64() targets.
- I haven't cleaned up all of the now-unused functions.
Some more of the generic parser could be removed too (integers and relocs
for example).
- insve.df needed a custom decoder to handle the implicit fourth operand that
was needed to make it parse correctly. The difficulty was that the matcher
expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this.
Reviewers: matheusalmeida, vmedic
Reviewed By: matheusalmeida
Differential Revision: http://llvm-reviews.chandlerc.com/D3222
llvm-svn: 205292
2014-04-01 12:35:28 +02:00
|
|
|
let Name = "GPR64AsmReg";
|
|
|
|
let PredicateMethod = "isGPRAsmReg";
|
2013-08-07 00:20:40 +02:00
|
|
|
}
|
|
|
|
|
[mips] Rewrite MipsAsmParser and MipsOperand.
Summary:
Highlights:
- Registers are resolved much later (by the render method).
Prior to that point, GPR32's/GPR64's are GPR's regardless of register
size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register
size or FR mode. Numeric registers can be anything.
- All registers are parsed the same way everywhere (even when handling
symbol aliasing)
- One consequence is that all registers can be specified numerically
almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing
but that can be easily resolved.
- Removes the need for the hasConsumedDollar hack
- Parenthesis and Bracket suffixes are handled generically
- Micromips instructions are parsed directly instead of going through the
standard encodings first.
- rdhwr accepts all 32 registers, and the following instructions that previously
xfailed now work:
ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d,
c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1
- Diagnostics involving registers point at the correct character (the $)
- There's only one kind of immediate in MipsOperand. LSA immediates are handled
by the predicate and renderer.
Lowlights:
- Hardcoded '$zero' in the div patterns is handled with a hack.
MipsOperand::isReg() will return true for a k_RegisterIndex token
with Index == 0 and getReg() will return ZERO for this case. Note that it
doesn't return ZERO_64 on isGP64() targets.
- I haven't cleaned up all of the now-unused functions.
Some more of the generic parser could be removed too (integers and relocs
for example).
- insve.df needed a custom decoder to handle the implicit fourth operand that
was needed to make it parse correctly. The difficulty was that the matcher
expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this.
Reviewers: matheusalmeida, vmedic
Reviewed By: matheusalmeida
Differential Revision: http://llvm-reviews.chandlerc.com/D3222
llvm-svn: 205292
2014-04-01 12:35:28 +02:00
|
|
|
def GPR32AsmOperand : MipsAsmRegOperand {
|
|
|
|
let Name = "GPR32AsmReg";
|
|
|
|
let PredicateMethod = "isGPRAsmReg";
|
2013-08-14 03:02:20 +02:00
|
|
|
}
|
|
|
|
|
2014-10-21 10:23:11 +02:00
|
|
|
def GPRMM16AsmOperand : MipsAsmRegOperand {
|
|
|
|
let Name = "GPRMM16AsmReg";
|
|
|
|
let PredicateMethod = "isMM16AsmReg";
|
|
|
|
}
|
|
|
|
|
2014-11-24 15:25:53 +01:00
|
|
|
def GPRMM16AsmOperandZero : MipsAsmRegOperand {
|
|
|
|
let Name = "GPRMM16AsmRegZero";
|
|
|
|
let PredicateMethod = "isMM16AsmRegZero";
|
|
|
|
}
|
|
|
|
|
2015-02-10 17:36:20 +01:00
|
|
|
def GPRMM16AsmOperandMoveP : MipsAsmRegOperand {
|
|
|
|
let Name = "GPRMM16AsmRegMoveP";
|
|
|
|
let PredicateMethod = "isMM16AsmRegMoveP";
|
|
|
|
}
|
|
|
|
|
[mips] Rewrite MipsAsmParser and MipsOperand.
Summary:
Highlights:
- Registers are resolved much later (by the render method).
Prior to that point, GPR32's/GPR64's are GPR's regardless of register
size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register
size or FR mode. Numeric registers can be anything.
- All registers are parsed the same way everywhere (even when handling
symbol aliasing)
- One consequence is that all registers can be specified numerically
almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing
but that can be easily resolved.
- Removes the need for the hasConsumedDollar hack
- Parenthesis and Bracket suffixes are handled generically
- Micromips instructions are parsed directly instead of going through the
standard encodings first.
- rdhwr accepts all 32 registers, and the following instructions that previously
xfailed now work:
ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d,
c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1
- Diagnostics involving registers point at the correct character (the $)
- There's only one kind of immediate in MipsOperand. LSA immediates are handled
by the predicate and renderer.
Lowlights:
- Hardcoded '$zero' in the div patterns is handled with a hack.
MipsOperand::isReg() will return true for a k_RegisterIndex token
with Index == 0 and getReg() will return ZERO for this case. Note that it
doesn't return ZERO_64 on isGP64() targets.
- I haven't cleaned up all of the now-unused functions.
Some more of the generic parser could be removed too (integers and relocs
for example).
- insve.df needed a custom decoder to handle the implicit fourth operand that
was needed to make it parse correctly. The difficulty was that the matcher
expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this.
Reviewers: matheusalmeida, vmedic
Reviewed By: matheusalmeida
Differential Revision: http://llvm-reviews.chandlerc.com/D3222
llvm-svn: 205292
2014-04-01 12:35:28 +02:00
|
|
|
def ACC64DSPAsmOperand : MipsAsmRegOperand {
|
|
|
|
let Name = "ACC64DSPAsmReg";
|
|
|
|
let PredicateMethod = "isACCAsmReg";
|
[mips] Rewrite MipsAsmParser and MipsOperand.
Summary:
Highlights:
- Registers are resolved much later (by the render method).
Prior to that point, GPR32's/GPR64's are GPR's regardless of register
size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register
size or FR mode. Numeric registers can be anything.
- All registers are parsed the same way everywhere (even when handling
symbol aliasing)
- One consequence is that all registers can be specified numerically
almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing
but that can be easily resolved.
- Removes the need for the hasConsumedDollar hack
- Parenthesis and Bracket suffixes are handled generically
- Micromips instructions are parsed directly instead of going through the
standard encodings first.
- rdhwr accepts all 32 registers, and the following instructions that previously
xfailed now work:
ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d,
c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1
- Diagnostics involving registers point at the correct character (the $)
- There's only one kind of immediate in MipsOperand. LSA immediates are handled
by the predicate and renderer.
Lowlights:
- Hardcoded '$zero' in the div patterns is handled with a hack.
MipsOperand::isReg() will return true for a k_RegisterIndex token
with Index == 0 and getReg() will return ZERO for this case. Note that it
doesn't return ZERO_64 on isGP64() targets.
- I haven't cleaned up all of the now-unused functions.
Some more of the generic parser could be removed too (integers and relocs
for example).
- insve.df needed a custom decoder to handle the implicit fourth operand that
was needed to make it parse correctly. The difficulty was that the matcher
expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this.
Reviewers: matheusalmeida, vmedic
Reviewed By: matheusalmeida
Differential Revision: http://llvm-reviews.chandlerc.com/D3222
llvm-svn: 205229
2014-03-31 19:43:46 +02:00
|
|
|
}
|
|
|
|
|
2014-03-31 20:51:43 +02:00
|
|
|
def HI32DSPAsmOperand : MipsAsmRegOperand {
|
[mips] Rewrite MipsAsmParser and MipsOperand.
Summary:
Highlights:
- Registers are resolved much later (by the render method).
Prior to that point, GPR32's/GPR64's are GPR's regardless of register
size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register
size or FR mode. Numeric registers can be anything.
- All registers are parsed the same way everywhere (even when handling
symbol aliasing)
- One consequence is that all registers can be specified numerically
almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing
but that can be easily resolved.
- Removes the need for the hasConsumedDollar hack
- Parenthesis and Bracket suffixes are handled generically
- Micromips instructions are parsed directly instead of going through the
standard encodings first.
- rdhwr accepts all 32 registers, and the following instructions that previously
xfailed now work:
ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d,
c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1
- Diagnostics involving registers point at the correct character (the $)
- There's only one kind of immediate in MipsOperand. LSA immediates are handled
by the predicate and renderer.
Lowlights:
- Hardcoded '$zero' in the div patterns is handled with a hack.
MipsOperand::isReg() will return true for a k_RegisterIndex token
with Index == 0 and getReg() will return ZERO for this case. Note that it
doesn't return ZERO_64 on isGP64() targets.
- I haven't cleaned up all of the now-unused functions.
Some more of the generic parser could be removed too (integers and relocs
for example).
- insve.df needed a custom decoder to handle the implicit fourth operand that
was needed to make it parse correctly. The difficulty was that the matcher
expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this.
Reviewers: matheusalmeida, vmedic
Reviewed By: matheusalmeida
Differential Revision: http://llvm-reviews.chandlerc.com/D3222
llvm-svn: 205292
2014-04-01 12:35:28 +02:00
|
|
|
let Name = "HI32DSPAsmReg";
|
|
|
|
let PredicateMethod = "isACCAsmReg";
|
|
|
|
}
|
|
|
|
|
|
|
|
def LO32DSPAsmOperand : MipsAsmRegOperand {
|
|
|
|
let Name = "LO32DSPAsmReg";
|
|
|
|
let PredicateMethod = "isACCAsmReg";
|
2013-08-14 03:02:20 +02:00
|
|
|
}
|
|
|
|
|
2013-06-19 12:14:36 +02:00
|
|
|
def CCRAsmOperand : MipsAsmRegOperand {
|
[mips] Rewrite MipsAsmParser and MipsOperand.
Summary:
Highlights:
- Registers are resolved much later (by the render method).
Prior to that point, GPR32's/GPR64's are GPR's regardless of register
size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register
size or FR mode. Numeric registers can be anything.
- All registers are parsed the same way everywhere (even when handling
symbol aliasing)
- One consequence is that all registers can be specified numerically
almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing
but that can be easily resolved.
- Removes the need for the hasConsumedDollar hack
- Parenthesis and Bracket suffixes are handled generically
- Micromips instructions are parsed directly instead of going through the
standard encodings first.
- rdhwr accepts all 32 registers, and the following instructions that previously
xfailed now work:
ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d,
c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1
- Diagnostics involving registers point at the correct character (the $)
- There's only one kind of immediate in MipsOperand. LSA immediates are handled
by the predicate and renderer.
Lowlights:
- Hardcoded '$zero' in the div patterns is handled with a hack.
MipsOperand::isReg() will return true for a k_RegisterIndex token
with Index == 0 and getReg() will return ZERO for this case. Note that it
doesn't return ZERO_64 on isGP64() targets.
- I haven't cleaned up all of the now-unused functions.
Some more of the generic parser could be removed too (integers and relocs
for example).
- insve.df needed a custom decoder to handle the implicit fourth operand that
was needed to make it parse correctly. The difficulty was that the matcher
expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this.
Reviewers: matheusalmeida, vmedic
Reviewed By: matheusalmeida
Differential Revision: http://llvm-reviews.chandlerc.com/D3222
llvm-svn: 205292
2014-04-01 12:35:28 +02:00
|
|
|
let Name = "CCRAsmReg";
|
2013-01-12 02:03:14 +01:00
|
|
|
}
|
|
|
|
|
2013-06-24 12:05:34 +02:00
|
|
|
def AFGR64AsmOperand : MipsAsmRegOperand {
|
[mips] Rewrite MipsAsmParser and MipsOperand.
Summary:
Highlights:
- Registers are resolved much later (by the render method).
Prior to that point, GPR32's/GPR64's are GPR's regardless of register
size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register
size or FR mode. Numeric registers can be anything.
- All registers are parsed the same way everywhere (even when handling
symbol aliasing)
- One consequence is that all registers can be specified numerically
almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing
but that can be easily resolved.
- Removes the need for the hasConsumedDollar hack
- Parenthesis and Bracket suffixes are handled generically
- Micromips instructions are parsed directly instead of going through the
standard encodings first.
- rdhwr accepts all 32 registers, and the following instructions that previously
xfailed now work:
ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d,
c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1
- Diagnostics involving registers point at the correct character (the $)
- There's only one kind of immediate in MipsOperand. LSA immediates are handled
by the predicate and renderer.
Lowlights:
- Hardcoded '$zero' in the div patterns is handled with a hack.
MipsOperand::isReg() will return true for a k_RegisterIndex token
with Index == 0 and getReg() will return ZERO for this case. Note that it
doesn't return ZERO_64 on isGP64() targets.
- I haven't cleaned up all of the now-unused functions.
Some more of the generic parser could be removed too (integers and relocs
for example).
- insve.df needed a custom decoder to handle the implicit fourth operand that
was needed to make it parse correctly. The difficulty was that the matcher
expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this.
Reviewers: matheusalmeida, vmedic
Reviewed By: matheusalmeida
Differential Revision: http://llvm-reviews.chandlerc.com/D3222
llvm-svn: 205292
2014-04-01 12:35:28 +02:00
|
|
|
let Name = "AFGR64AsmReg";
|
|
|
|
let PredicateMethod = "isFGRAsmReg";
|
2013-06-24 12:05:34 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
def FGR64AsmOperand : MipsAsmRegOperand {
|
[mips] Rewrite MipsAsmParser and MipsOperand.
Summary:
Highlights:
- Registers are resolved much later (by the render method).
Prior to that point, GPR32's/GPR64's are GPR's regardless of register
size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register
size or FR mode. Numeric registers can be anything.
- All registers are parsed the same way everywhere (even when handling
symbol aliasing)
- One consequence is that all registers can be specified numerically
almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing
but that can be easily resolved.
- Removes the need for the hasConsumedDollar hack
- Parenthesis and Bracket suffixes are handled generically
- Micromips instructions are parsed directly instead of going through the
standard encodings first.
- rdhwr accepts all 32 registers, and the following instructions that previously
xfailed now work:
ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d,
c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1
- Diagnostics involving registers point at the correct character (the $)
- There's only one kind of immediate in MipsOperand. LSA immediates are handled
by the predicate and renderer.
Lowlights:
- Hardcoded '$zero' in the div patterns is handled with a hack.
MipsOperand::isReg() will return true for a k_RegisterIndex token
with Index == 0 and getReg() will return ZERO for this case. Note that it
doesn't return ZERO_64 on isGP64() targets.
- I haven't cleaned up all of the now-unused functions.
Some more of the generic parser could be removed too (integers and relocs
for example).
- insve.df needed a custom decoder to handle the implicit fourth operand that
was needed to make it parse correctly. The difficulty was that the matcher
expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this.
Reviewers: matheusalmeida, vmedic
Reviewed By: matheusalmeida
Differential Revision: http://llvm-reviews.chandlerc.com/D3222
llvm-svn: 205292
2014-04-01 12:35:28 +02:00
|
|
|
let Name = "FGR64AsmReg";
|
|
|
|
let PredicateMethod = "isFGRAsmReg";
|
2013-06-24 12:05:34 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
def FGR32AsmOperand : MipsAsmRegOperand {
|
[mips] Rewrite MipsAsmParser and MipsOperand.
Summary:
Highlights:
- Registers are resolved much later (by the render method).
Prior to that point, GPR32's/GPR64's are GPR's regardless of register
size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register
size or FR mode. Numeric registers can be anything.
- All registers are parsed the same way everywhere (even when handling
symbol aliasing)
- One consequence is that all registers can be specified numerically
almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing
but that can be easily resolved.
- Removes the need for the hasConsumedDollar hack
- Parenthesis and Bracket suffixes are handled generically
- Micromips instructions are parsed directly instead of going through the
standard encodings first.
- rdhwr accepts all 32 registers, and the following instructions that previously
xfailed now work:
ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d,
c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1
- Diagnostics involving registers point at the correct character (the $)
- There's only one kind of immediate in MipsOperand. LSA immediates are handled
by the predicate and renderer.
Lowlights:
- Hardcoded '$zero' in the div patterns is handled with a hack.
MipsOperand::isReg() will return true for a k_RegisterIndex token
with Index == 0 and getReg() will return ZERO for this case. Note that it
doesn't return ZERO_64 on isGP64() targets.
- I haven't cleaned up all of the now-unused functions.
Some more of the generic parser could be removed too (integers and relocs
for example).
- insve.df needed a custom decoder to handle the implicit fourth operand that
was needed to make it parse correctly. The difficulty was that the matcher
expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this.
Reviewers: matheusalmeida, vmedic
Reviewed By: matheusalmeida
Differential Revision: http://llvm-reviews.chandlerc.com/D3222
llvm-svn: 205292
2014-04-01 12:35:28 +02:00
|
|
|
let Name = "FGR32AsmReg";
|
|
|
|
let PredicateMethod = "isFGRAsmReg";
|
2013-06-24 12:05:34 +02:00
|
|
|
}
|
|
|
|
|
2013-08-21 00:58:56 +02:00
|
|
|
def FGRH32AsmOperand : MipsAsmRegOperand {
|
[mips] Rewrite MipsAsmParser and MipsOperand.
Summary:
Highlights:
- Registers are resolved much later (by the render method).
Prior to that point, GPR32's/GPR64's are GPR's regardless of register
size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register
size or FR mode. Numeric registers can be anything.
- All registers are parsed the same way everywhere (even when handling
symbol aliasing)
- One consequence is that all registers can be specified numerically
almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing
but that can be easily resolved.
- Removes the need for the hasConsumedDollar hack
- Parenthesis and Bracket suffixes are handled generically
- Micromips instructions are parsed directly instead of going through the
standard encodings first.
- rdhwr accepts all 32 registers, and the following instructions that previously
xfailed now work:
ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d,
c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1
- Diagnostics involving registers point at the correct character (the $)
- There's only one kind of immediate in MipsOperand. LSA immediates are handled
by the predicate and renderer.
Lowlights:
- Hardcoded '$zero' in the div patterns is handled with a hack.
MipsOperand::isReg() will return true for a k_RegisterIndex token
with Index == 0 and getReg() will return ZERO for this case. Note that it
doesn't return ZERO_64 on isGP64() targets.
- I haven't cleaned up all of the now-unused functions.
Some more of the generic parser could be removed too (integers and relocs
for example).
- insve.df needed a custom decoder to handle the implicit fourth operand that
was needed to make it parse correctly. The difficulty was that the matcher
expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this.
Reviewers: matheusalmeida, vmedic
Reviewed By: matheusalmeida
Differential Revision: http://llvm-reviews.chandlerc.com/D3222
llvm-svn: 205292
2014-04-01 12:35:28 +02:00
|
|
|
let Name = "FGRH32AsmReg";
|
|
|
|
let PredicateMethod = "isFGRAsmReg";
|
2013-08-21 00:58:56 +02:00
|
|
|
}
|
|
|
|
|
2013-07-30 12:12:14 +02:00
|
|
|
def FCCRegsAsmOperand : MipsAsmRegOperand {
|
[mips] Rewrite MipsAsmParser and MipsOperand.
Summary:
Highlights:
- Registers are resolved much later (by the render method).
Prior to that point, GPR32's/GPR64's are GPR's regardless of register
size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register
size or FR mode. Numeric registers can be anything.
- All registers are parsed the same way everywhere (even when handling
symbol aliasing)
- One consequence is that all registers can be specified numerically
almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing
but that can be easily resolved.
- Removes the need for the hasConsumedDollar hack
- Parenthesis and Bracket suffixes are handled generically
- Micromips instructions are parsed directly instead of going through the
standard encodings first.
- rdhwr accepts all 32 registers, and the following instructions that previously
xfailed now work:
ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d,
c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1
- Diagnostics involving registers point at the correct character (the $)
- There's only one kind of immediate in MipsOperand. LSA immediates are handled
by the predicate and renderer.
Lowlights:
- Hardcoded '$zero' in the div patterns is handled with a hack.
MipsOperand::isReg() will return true for a k_RegisterIndex token
with Index == 0 and getReg() will return ZERO for this case. Note that it
doesn't return ZERO_64 on isGP64() targets.
- I haven't cleaned up all of the now-unused functions.
Some more of the generic parser could be removed too (integers and relocs
for example).
- insve.df needed a custom decoder to handle the implicit fourth operand that
was needed to make it parse correctly. The difficulty was that the matcher
expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this.
Reviewers: matheusalmeida, vmedic
Reviewed By: matheusalmeida
Differential Revision: http://llvm-reviews.chandlerc.com/D3222
llvm-svn: 205292
2014-04-01 12:35:28 +02:00
|
|
|
let Name = "FCCAsmReg";
|
2013-09-26 01:50:44 +02:00
|
|
|
}
|
|
|
|
|
[mips] Rewrite MipsAsmParser and MipsOperand.
Summary:
Highlights:
- Registers are resolved much later (by the render method).
Prior to that point, GPR32's/GPR64's are GPR's regardless of register
size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register
size or FR mode. Numeric registers can be anything.
- All registers are parsed the same way everywhere (even when handling
symbol aliasing)
- One consequence is that all registers can be specified numerically
almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing
but that can be easily resolved.
- Removes the need for the hasConsumedDollar hack
- Parenthesis and Bracket suffixes are handled generically
- Micromips instructions are parsed directly instead of going through the
standard encodings first.
- rdhwr accepts all 32 registers, and the following instructions that previously
xfailed now work:
ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d,
c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1
- Diagnostics involving registers point at the correct character (the $)
- There's only one kind of immediate in MipsOperand. LSA immediates are handled
by the predicate and renderer.
Lowlights:
- Hardcoded '$zero' in the div patterns is handled with a hack.
MipsOperand::isReg() will return true for a k_RegisterIndex token
with Index == 0 and getReg() will return ZERO for this case. Note that it
doesn't return ZERO_64 on isGP64() targets.
- I haven't cleaned up all of the now-unused functions.
Some more of the generic parser could be removed too (integers and relocs
for example).
- insve.df needed a custom decoder to handle the implicit fourth operand that
was needed to make it parse correctly. The difficulty was that the matcher
expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this.
Reviewers: matheusalmeida, vmedic
Reviewed By: matheusalmeida
Differential Revision: http://llvm-reviews.chandlerc.com/D3222
llvm-svn: 205292
2014-04-01 12:35:28 +02:00
|
|
|
def MSA128AsmOperand : MipsAsmRegOperand {
|
|
|
|
let Name = "MSA128AsmReg";
|
2013-09-26 01:50:44 +02:00
|
|
|
}
|
|
|
|
|
[mips] Rewrite MipsAsmParser and MipsOperand.
Summary:
Highlights:
- Registers are resolved much later (by the render method).
Prior to that point, GPR32's/GPR64's are GPR's regardless of register
size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register
size or FR mode. Numeric registers can be anything.
- All registers are parsed the same way everywhere (even when handling
symbol aliasing)
- One consequence is that all registers can be specified numerically
almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing
but that can be easily resolved.
- Removes the need for the hasConsumedDollar hack
- Parenthesis and Bracket suffixes are handled generically
- Micromips instructions are parsed directly instead of going through the
standard encodings first.
- rdhwr accepts all 32 registers, and the following instructions that previously
xfailed now work:
ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d,
c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1
- Diagnostics involving registers point at the correct character (the $)
- There's only one kind of immediate in MipsOperand. LSA immediates are handled
by the predicate and renderer.
Lowlights:
- Hardcoded '$zero' in the div patterns is handled with a hack.
MipsOperand::isReg() will return true for a k_RegisterIndex token
with Index == 0 and getReg() will return ZERO for this case. Note that it
doesn't return ZERO_64 on isGP64() targets.
- I haven't cleaned up all of the now-unused functions.
Some more of the generic parser could be removed too (integers and relocs
for example).
- insve.df needed a custom decoder to handle the implicit fourth operand that
was needed to make it parse correctly. The difficulty was that the matcher
expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this.
Reviewers: matheusalmeida, vmedic
Reviewed By: matheusalmeida
Differential Revision: http://llvm-reviews.chandlerc.com/D3222
llvm-svn: 205292
2014-04-01 12:35:28 +02:00
|
|
|
def MSACtrlAsmOperand : MipsAsmRegOperand {
|
|
|
|
let Name = "MSACtrlAsmReg";
|
2013-10-21 14:26:50 +02:00
|
|
|
}
|
|
|
|
|
2013-08-07 01:08:38 +02:00
|
|
|
def GPR32Opnd : RegisterOperand<GPR32> {
|
|
|
|
let ParserMatchClass = GPR32AsmOperand;
|
2013-01-12 02:03:14 +01:00
|
|
|
}
|
|
|
|
|
2014-10-21 10:23:11 +02:00
|
|
|
def GPRMM16Opnd : RegisterOperand<GPRMM16> {
|
|
|
|
let ParserMatchClass = GPRMM16AsmOperand;
|
|
|
|
}
|
|
|
|
|
2014-11-24 15:25:53 +01:00
|
|
|
def GPRMM16OpndZero : RegisterOperand<GPRMM16Zero> {
|
|
|
|
let ParserMatchClass = GPRMM16AsmOperandZero;
|
|
|
|
}
|
|
|
|
|
2015-02-10 17:36:20 +01:00
|
|
|
def GPRMM16OpndMoveP : RegisterOperand<GPRMM16MoveP> {
|
|
|
|
let ParserMatchClass = GPRMM16AsmOperandMoveP;
|
|
|
|
}
|
|
|
|
|
2013-08-07 01:08:38 +02:00
|
|
|
def GPR64Opnd : RegisterOperand<GPR64> {
|
|
|
|
let ParserMatchClass = GPR64AsmOperand;
|
2013-01-12 02:03:14 +01:00
|
|
|
}
|
|
|
|
|
2013-08-14 02:53:38 +02:00
|
|
|
def DSPROpnd : RegisterOperand<DSPR> {
|
|
|
|
let ParserMatchClass = GPR32AsmOperand;
|
|
|
|
}
|
|
|
|
|
2013-07-26 20:50:42 +02:00
|
|
|
def CCROpnd : RegisterOperand<CCR> {
|
2013-01-12 02:03:14 +01:00
|
|
|
let ParserMatchClass = CCRAsmOperand;
|
|
|
|
}
|
|
|
|
|
2013-06-19 12:14:36 +02:00
|
|
|
def HWRegsAsmOperand : MipsAsmRegOperand {
|
[mips] Rewrite MipsAsmParser and MipsOperand.
Summary:
Highlights:
- Registers are resolved much later (by the render method).
Prior to that point, GPR32's/GPR64's are GPR's regardless of register
size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register
size or FR mode. Numeric registers can be anything.
- All registers are parsed the same way everywhere (even when handling
symbol aliasing)
- One consequence is that all registers can be specified numerically
almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing
but that can be easily resolved.
- Removes the need for the hasConsumedDollar hack
- Parenthesis and Bracket suffixes are handled generically
- Micromips instructions are parsed directly instead of going through the
standard encodings first.
- rdhwr accepts all 32 registers, and the following instructions that previously
xfailed now work:
ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d,
c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1
- Diagnostics involving registers point at the correct character (the $)
- There's only one kind of immediate in MipsOperand. LSA immediates are handled
by the predicate and renderer.
Lowlights:
- Hardcoded '$zero' in the div patterns is handled with a hack.
MipsOperand::isReg() will return true for a k_RegisterIndex token
with Index == 0 and getReg() will return ZERO for this case. Note that it
doesn't return ZERO_64 on isGP64() targets.
- I haven't cleaned up all of the now-unused functions.
Some more of the generic parser could be removed too (integers and relocs
for example).
- insve.df needed a custom decoder to handle the implicit fourth operand that
was needed to make it parse correctly. The difficulty was that the matcher
expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this.
Reviewers: matheusalmeida, vmedic
Reviewed By: matheusalmeida
Differential Revision: http://llvm-reviews.chandlerc.com/D3222
llvm-svn: 205292
2014-04-01 12:35:28 +02:00
|
|
|
let Name = "HWRegsAsmReg";
|
2013-01-12 02:03:14 +01:00
|
|
|
}
|
|
|
|
|
2013-09-16 12:29:42 +02:00
|
|
|
def COP2AsmOperand : MipsAsmRegOperand {
|
[mips] Rewrite MipsAsmParser and MipsOperand.
Summary:
Highlights:
- Registers are resolved much later (by the render method).
Prior to that point, GPR32's/GPR64's are GPR's regardless of register
size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register
size or FR mode. Numeric registers can be anything.
- All registers are parsed the same way everywhere (even when handling
symbol aliasing)
- One consequence is that all registers can be specified numerically
almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing
but that can be easily resolved.
- Removes the need for the hasConsumedDollar hack
- Parenthesis and Bracket suffixes are handled generically
- Micromips instructions are parsed directly instead of going through the
standard encodings first.
- rdhwr accepts all 32 registers, and the following instructions that previously
xfailed now work:
ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d,
c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1
- Diagnostics involving registers point at the correct character (the $)
- There's only one kind of immediate in MipsOperand. LSA immediates are handled
by the predicate and renderer.
Lowlights:
- Hardcoded '$zero' in the div patterns is handled with a hack.
MipsOperand::isReg() will return true for a k_RegisterIndex token
with Index == 0 and getReg() will return ZERO for this case. Note that it
doesn't return ZERO_64 on isGP64() targets.
- I haven't cleaned up all of the now-unused functions.
Some more of the generic parser could be removed too (integers and relocs
for example).
- insve.df needed a custom decoder to handle the implicit fourth operand that
was needed to make it parse correctly. The difficulty was that the matcher
expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this.
Reviewers: matheusalmeida, vmedic
Reviewed By: matheusalmeida
Differential Revision: http://llvm-reviews.chandlerc.com/D3222
llvm-svn: 205292
2014-04-01 12:35:28 +02:00
|
|
|
let Name = "COP2AsmReg";
|
2013-09-16 12:29:42 +02:00
|
|
|
}
|
|
|
|
|
2014-05-08 15:02:11 +02:00
|
|
|
def COP3AsmOperand : MipsAsmRegOperand {
|
|
|
|
let Name = "COP3AsmReg";
|
|
|
|
}
|
|
|
|
|
2013-07-26 20:50:42 +02:00
|
|
|
def HWRegsOpnd : RegisterOperand<HWRegs> {
|
2013-01-12 02:03:14 +01:00
|
|
|
let ParserMatchClass = HWRegsAsmOperand;
|
|
|
|
}
|
|
|
|
|
2013-08-08 23:54:26 +02:00
|
|
|
def AFGR64Opnd : RegisterOperand<AFGR64> {
|
2013-06-24 12:05:34 +02:00
|
|
|
let ParserMatchClass = AFGR64AsmOperand;
|
|
|
|
}
|
|
|
|
|
2013-08-08 23:54:26 +02:00
|
|
|
def FGR64Opnd : RegisterOperand<FGR64> {
|
2013-06-24 12:05:34 +02:00
|
|
|
let ParserMatchClass = FGR64AsmOperand;
|
|
|
|
}
|
|
|
|
|
2013-08-08 23:54:26 +02:00
|
|
|
def FGR32Opnd : RegisterOperand<FGR32> {
|
2013-06-24 12:05:34 +02:00
|
|
|
let ParserMatchClass = FGR32AsmOperand;
|
2013-07-30 12:12:14 +02:00
|
|
|
}
|
|
|
|
|
2014-06-12 15:39:06 +02:00
|
|
|
def FGRCCOpnd : RegisterOperand<FGRCC> {
|
|
|
|
// The assembler doesn't use register classes so we can re-use
|
|
|
|
// FGR32AsmOperand.
|
|
|
|
let ParserMatchClass = FGR32AsmOperand;
|
|
|
|
}
|
|
|
|
|
2013-08-21 00:58:56 +02:00
|
|
|
def FGRH32Opnd : RegisterOperand<FGRH32> {
|
|
|
|
let ParserMatchClass = FGRH32AsmOperand;
|
|
|
|
}
|
|
|
|
|
2013-07-30 12:12:14 +02:00
|
|
|
def FCCRegsOpnd : RegisterOperand<FCC> {
|
|
|
|
let ParserMatchClass = FCCRegsAsmOperand;
|
2013-08-07 00:20:40 +02:00
|
|
|
}
|
|
|
|
|
2013-08-14 03:02:20 +02:00
|
|
|
def LO32DSPOpnd : RegisterOperand<LO32DSP> {
|
|
|
|
let ParserMatchClass = LO32DSPAsmOperand;
|
|
|
|
}
|
|
|
|
|
|
|
|
def HI32DSPOpnd : RegisterOperand<HI32DSP> {
|
|
|
|
let ParserMatchClass = HI32DSPAsmOperand;
|
|
|
|
}
|
|
|
|
|
2013-08-08 23:54:26 +02:00
|
|
|
def ACC64DSPOpnd : RegisterOperand<ACC64DSP> {
|
|
|
|
let ParserMatchClass = ACC64DSPAsmOperand;
|
2013-08-07 00:20:40 +02:00
|
|
|
}
|
2013-09-16 12:29:42 +02:00
|
|
|
|
|
|
|
def COP2Opnd : RegisterOperand<COP2> {
|
|
|
|
let ParserMatchClass = COP2AsmOperand;
|
|
|
|
}
|
2013-09-26 01:50:44 +02:00
|
|
|
|
2014-05-08 15:02:11 +02:00
|
|
|
def COP3Opnd : RegisterOperand<COP3> {
|
|
|
|
let ParserMatchClass = COP3AsmOperand;
|
|
|
|
}
|
|
|
|
|
2013-09-26 01:50:44 +02:00
|
|
|
def MSA128BOpnd : RegisterOperand<MSA128B> {
|
[mips] Rewrite MipsAsmParser and MipsOperand.
Summary:
Highlights:
- Registers are resolved much later (by the render method).
Prior to that point, GPR32's/GPR64's are GPR's regardless of register
size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register
size or FR mode. Numeric registers can be anything.
- All registers are parsed the same way everywhere (even when handling
symbol aliasing)
- One consequence is that all registers can be specified numerically
almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing
but that can be easily resolved.
- Removes the need for the hasConsumedDollar hack
- Parenthesis and Bracket suffixes are handled generically
- Micromips instructions are parsed directly instead of going through the
standard encodings first.
- rdhwr accepts all 32 registers, and the following instructions that previously
xfailed now work:
ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d,
c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1
- Diagnostics involving registers point at the correct character (the $)
- There's only one kind of immediate in MipsOperand. LSA immediates are handled
by the predicate and renderer.
Lowlights:
- Hardcoded '$zero' in the div patterns is handled with a hack.
MipsOperand::isReg() will return true for a k_RegisterIndex token
with Index == 0 and getReg() will return ZERO for this case. Note that it
doesn't return ZERO_64 on isGP64() targets.
- I haven't cleaned up all of the now-unused functions.
Some more of the generic parser could be removed too (integers and relocs
for example).
- insve.df needed a custom decoder to handle the implicit fourth operand that
was needed to make it parse correctly. The difficulty was that the matcher
expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this.
Reviewers: matheusalmeida, vmedic
Reviewed By: matheusalmeida
Differential Revision: http://llvm-reviews.chandlerc.com/D3222
llvm-svn: 205292
2014-04-01 12:35:28 +02:00
|
|
|
let ParserMatchClass = MSA128AsmOperand;
|
2013-09-26 01:50:44 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
def MSA128HOpnd : RegisterOperand<MSA128H> {
|
[mips] Rewrite MipsAsmParser and MipsOperand.
Summary:
Highlights:
- Registers are resolved much later (by the render method).
Prior to that point, GPR32's/GPR64's are GPR's regardless of register
size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register
size or FR mode. Numeric registers can be anything.
- All registers are parsed the same way everywhere (even when handling
symbol aliasing)
- One consequence is that all registers can be specified numerically
almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing
but that can be easily resolved.
- Removes the need for the hasConsumedDollar hack
- Parenthesis and Bracket suffixes are handled generically
- Micromips instructions are parsed directly instead of going through the
standard encodings first.
- rdhwr accepts all 32 registers, and the following instructions that previously
xfailed now work:
ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d,
c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1
- Diagnostics involving registers point at the correct character (the $)
- There's only one kind of immediate in MipsOperand. LSA immediates are handled
by the predicate and renderer.
Lowlights:
- Hardcoded '$zero' in the div patterns is handled with a hack.
MipsOperand::isReg() will return true for a k_RegisterIndex token
with Index == 0 and getReg() will return ZERO for this case. Note that it
doesn't return ZERO_64 on isGP64() targets.
- I haven't cleaned up all of the now-unused functions.
Some more of the generic parser could be removed too (integers and relocs
for example).
- insve.df needed a custom decoder to handle the implicit fourth operand that
was needed to make it parse correctly. The difficulty was that the matcher
expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this.
Reviewers: matheusalmeida, vmedic
Reviewed By: matheusalmeida
Differential Revision: http://llvm-reviews.chandlerc.com/D3222
llvm-svn: 205292
2014-04-01 12:35:28 +02:00
|
|
|
let ParserMatchClass = MSA128AsmOperand;
|
2013-09-26 01:50:44 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
def MSA128WOpnd : RegisterOperand<MSA128W> {
|
[mips] Rewrite MipsAsmParser and MipsOperand.
Summary:
Highlights:
- Registers are resolved much later (by the render method).
Prior to that point, GPR32's/GPR64's are GPR's regardless of register
size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register
size or FR mode. Numeric registers can be anything.
- All registers are parsed the same way everywhere (even when handling
symbol aliasing)
- One consequence is that all registers can be specified numerically
almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing
but that can be easily resolved.
- Removes the need for the hasConsumedDollar hack
- Parenthesis and Bracket suffixes are handled generically
- Micromips instructions are parsed directly instead of going through the
standard encodings first.
- rdhwr accepts all 32 registers, and the following instructions that previously
xfailed now work:
ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d,
c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1
- Diagnostics involving registers point at the correct character (the $)
- There's only one kind of immediate in MipsOperand. LSA immediates are handled
by the predicate and renderer.
Lowlights:
- Hardcoded '$zero' in the div patterns is handled with a hack.
MipsOperand::isReg() will return true for a k_RegisterIndex token
with Index == 0 and getReg() will return ZERO for this case. Note that it
doesn't return ZERO_64 on isGP64() targets.
- I haven't cleaned up all of the now-unused functions.
Some more of the generic parser could be removed too (integers and relocs
for example).
- insve.df needed a custom decoder to handle the implicit fourth operand that
was needed to make it parse correctly. The difficulty was that the matcher
expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this.
Reviewers: matheusalmeida, vmedic
Reviewed By: matheusalmeida
Differential Revision: http://llvm-reviews.chandlerc.com/D3222
llvm-svn: 205292
2014-04-01 12:35:28 +02:00
|
|
|
let ParserMatchClass = MSA128AsmOperand;
|
2013-09-26 01:50:44 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
def MSA128DOpnd : RegisterOperand<MSA128D> {
|
[mips] Rewrite MipsAsmParser and MipsOperand.
Summary:
Highlights:
- Registers are resolved much later (by the render method).
Prior to that point, GPR32's/GPR64's are GPR's regardless of register
size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register
size or FR mode. Numeric registers can be anything.
- All registers are parsed the same way everywhere (even when handling
symbol aliasing)
- One consequence is that all registers can be specified numerically
almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing
but that can be easily resolved.
- Removes the need for the hasConsumedDollar hack
- Parenthesis and Bracket suffixes are handled generically
- Micromips instructions are parsed directly instead of going through the
standard encodings first.
- rdhwr accepts all 32 registers, and the following instructions that previously
xfailed now work:
ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d,
c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1
- Diagnostics involving registers point at the correct character (the $)
- There's only one kind of immediate in MipsOperand. LSA immediates are handled
by the predicate and renderer.
Lowlights:
- Hardcoded '$zero' in the div patterns is handled with a hack.
MipsOperand::isReg() will return true for a k_RegisterIndex token
with Index == 0 and getReg() will return ZERO for this case. Note that it
doesn't return ZERO_64 on isGP64() targets.
- I haven't cleaned up all of the now-unused functions.
Some more of the generic parser could be removed too (integers and relocs
for example).
- insve.df needed a custom decoder to handle the implicit fourth operand that
was needed to make it parse correctly. The difficulty was that the matcher
expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this.
Reviewers: matheusalmeida, vmedic
Reviewed By: matheusalmeida
Differential Revision: http://llvm-reviews.chandlerc.com/D3222
llvm-svn: 205292
2014-04-01 12:35:28 +02:00
|
|
|
let ParserMatchClass = MSA128AsmOperand;
|
2013-09-26 01:50:44 +02:00
|
|
|
}
|
|
|
|
|
2013-10-21 14:26:50 +02:00
|
|
|
def MSA128CROpnd : RegisterOperand<MSACtrl> {
|
[mips] Rewrite MipsAsmParser and MipsOperand.
Summary:
Highlights:
- Registers are resolved much later (by the render method).
Prior to that point, GPR32's/GPR64's are GPR's regardless of register
size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register
size or FR mode. Numeric registers can be anything.
- All registers are parsed the same way everywhere (even when handling
symbol aliasing)
- One consequence is that all registers can be specified numerically
almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing
but that can be easily resolved.
- Removes the need for the hasConsumedDollar hack
- Parenthesis and Bracket suffixes are handled generically
- Micromips instructions are parsed directly instead of going through the
standard encodings first.
- rdhwr accepts all 32 registers, and the following instructions that previously
xfailed now work:
ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d,
c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1
- Diagnostics involving registers point at the correct character (the $)
- There's only one kind of immediate in MipsOperand. LSA immediates are handled
by the predicate and renderer.
Lowlights:
- Hardcoded '$zero' in the div patterns is handled with a hack.
MipsOperand::isReg() will return true for a k_RegisterIndex token
with Index == 0 and getReg() will return ZERO for this case. Note that it
doesn't return ZERO_64 on isGP64() targets.
- I haven't cleaned up all of the now-unused functions.
Some more of the generic parser could be removed too (integers and relocs
for example).
- insve.df needed a custom decoder to handle the implicit fourth operand that
was needed to make it parse correctly. The difficulty was that the matcher
expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this.
Reviewers: matheusalmeida, vmedic
Reviewed By: matheusalmeida
Differential Revision: http://llvm-reviews.chandlerc.com/D3222
llvm-svn: 205292
2014-04-01 12:35:28 +02:00
|
|
|
let ParserMatchClass = MSACtrlAsmOperand;
|
2013-10-21 14:26:50 +02:00
|
|
|
}
|