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llvm-mirror/test/CodeGen/Hexagon/expand-condsets-def-undef.mir

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[Hexagon] Account for <def,read-undef> when validating moves for predication llvm-svn: 286009
2016-11-04 21:41:03 +01:00
# RUN: llc -march=hexagon -run-pass expand-condsets -o - %s -verify-machineinstrs | FileCheck %s
# CHECK-LABEL: name: fred
# Make sure that <def,read-undef> is accounted for when validating moves
[Hexagon] Separate Hexagon subreg indices for different register classes For pairs of 32-bit registers: isub_lo, isub_hi. For pairs of vector registers: vsub_lo, vsub_hi. Add generic subreg indices: ps_sub_lo, ps_sub_hi, and a function HexagonRegisterInfo::getHexagonSubRegIndex(RegClass, GenericSubreg) that returns the appropriate subreg index for RegClass. llvm-svn: 286377
2016-11-09 17:19:08 +01:00
# during predication. In the code below, %2.isub_hi is invalidated
[Hexagon] Account for <def,read-undef> when validating moves for predication llvm-svn: 286009
2016-11-04 21:41:03 +01:00
# by the C2_mux instruction, and so predicating the A2_addi as an argument
# to the C2_muxir should not happen.
--- |
define void @fred() { ret void }
...
---
name: fred
tracksRegLiveness: true
registers:
- { id: 0, class: predregs }
- { id: 1, class: intregs }
- { id: 2, class: doubleregs }
- { id: 3, class: intregs }
liveins:
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-01-31 23:04:26 +01:00
- { reg: '$p0', virtual-reg: '%0' }
- { reg: '$r0', virtual-reg: '%1' }
- { reg: '$d0', virtual-reg: '%2' }
[Hexagon] Account for <def,read-undef> when validating moves for predication llvm-svn: 286009
2016-11-04 21:41:03 +01:00
body: |
bb.0:
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-01-31 23:04:26 +01:00
liveins: $r0, $d0, $p0
%0 = COPY $p0
%1 = COPY $r0
%2 = COPY $d0
[Hexagon] Account for <def,read-undef> when validating moves for predication llvm-svn: 286009
2016-11-04 21:41:03 +01:00
; Check that this instruction is unchanged (remains unpredicated)
MIR: Print the register class or bank in vreg defs This updates the MIRPrinter to include the regclass when printing virtual register defs, which is already valid syntax for the parser. That is, given 64 bit %0 and %1 in a "gpr" regbank, %1(s64) = COPY %0(s64) would now be written as %1:gpr(s64) = COPY %0(s64) While this change alone introduces a bit of redundancy with the registers block, it allows us to update the tests to be more concise and understandable and brings us closer to being able to remove the registers block completely. Note: We generally only print the class in defs, but there is one exception. If there are uses without any defs whatsoever, we'll print the class on all uses. I'm not completely convinced this comes up in meaningful machine IR, but for now the MIRParser and MachineVerifier both accept that kind of stuff, so we don't want to have a situation where we can print something we can't parse. llvm-svn: 316479
2017-10-24 20:04:54 +02:00
; CHECK: %3:intregs = A2_addi %2.isub_hi, 1
[Hexagon] Separate Hexagon subreg indices for different register classes For pairs of 32-bit registers: isub_lo, isub_hi. For pairs of vector registers: vsub_lo, vsub_hi. Add generic subreg indices: ps_sub_lo, ps_sub_hi, and a function HexagonRegisterInfo::getHexagonSubRegIndex(RegClass, GenericSubreg) that returns the appropriate subreg index for RegClass. llvm-svn: 286377
2016-11-09 17:19:08 +01:00
%3 = A2_addi %2.isub_hi, 1
undef %2.isub_lo = C2_mux %0, %2.isub_lo, %1
%2.isub_hi = C2_muxir %0, %3, 0
[Hexagon] Account for <def,read-undef> when validating moves for predication llvm-svn: 286009
2016-11-04 21:41:03 +01:00
...
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