2012-12-11 22:25:42 +01:00
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//===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief The AMDGPU target machine contains all of the hardware specific
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/// information needed to emit code for R600 and SI GPUs.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUTargetMachine.h"
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2015-12-10 03:13:01 +01:00
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#include "AMDGPUTargetObjectFile.h"
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2012-12-11 22:25:42 +01:00
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#include "AMDGPU.h"
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2015-01-31 12:17:59 +01:00
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#include "AMDGPUTargetTransformInfo.h"
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2012-12-11 22:25:42 +01:00
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#include "R600ISelLowering.h"
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#include "R600InstrInfo.h"
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2013-03-05 19:41:32 +01:00
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#include "R600MachineScheduler.h"
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2012-12-11 22:25:42 +01:00
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#include "SIISelLowering.h"
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#include "SIInstrInfo.h"
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#include "llvm/Analysis/Passes.h"
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2016-04-14 21:09:28 +02:00
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#include "llvm/CodeGen/GlobalISel/IRTranslator.h"
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2012-12-11 22:25:42 +01:00
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#include "llvm/CodeGen/MachineFunctionAnalysis.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/Passes.h"
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2016-05-10 05:21:59 +02:00
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#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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2014-01-13 10:26:24 +01:00
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#include "llvm/IR/Verifier.h"
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2012-12-11 22:25:42 +01:00
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#include "llvm/MC/MCAsmInfo.h"
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2015-02-13 11:01:29 +01:00
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#include "llvm/IR/LegacyPassManager.h"
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2012-12-11 22:25:42 +01:00
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_os_ostream.h"
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#include "llvm/Transforms/IPO.h"
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#include "llvm/Transforms/Scalar.h"
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#include <llvm/CodeGen/Passes.h>
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using namespace llvm;
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2015-06-13 05:28:10 +02:00
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extern "C" void LLVMInitializeAMDGPUTarget() {
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2012-12-11 22:25:42 +01:00
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// Register the target
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2015-02-11 18:11:50 +01:00
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RegisterTargetMachine<R600TargetMachine> X(TheAMDGPUTarget);
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2015-01-06 19:00:21 +01:00
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RegisterTargetMachine<GCNTargetMachine> Y(TheGCNTarget);
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2015-10-02 00:10:03 +02:00
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PassRegistry *PR = PassRegistry::getPassRegistry();
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2015-10-12 19:43:59 +02:00
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initializeSILowerI1CopiesPass(*PR);
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2015-11-03 23:30:13 +01:00
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initializeSIFixSGPRCopiesPass(*PR);
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2015-10-12 19:43:59 +02:00
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initializeSIFoldOperandsPass(*PR);
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2015-10-07 02:42:53 +02:00
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initializeSIFixControlFlowLiveIntervalsPass(*PR);
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initializeSILoadStoreOptimizerPass(*PR);
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2015-11-06 19:01:57 +01:00
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initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
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2015-12-15 21:55:55 +01:00
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initializeAMDGPUAnnotateUniformValuesPass(*PR);
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2016-01-30 06:19:45 +01:00
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initializeAMDGPUPromoteAllocaPass(*PR);
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2016-01-20 16:48:27 +01:00
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initializeSIAnnotateControlFlowPass(*PR);
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2016-05-10 20:33:41 +02:00
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initializeSIDebuggerInsertNopsPass(*PR);
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2016-02-05 18:42:38 +01:00
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initializeSIInsertWaitsPass(*PR);
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2016-03-21 21:28:33 +01:00
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initializeSIWholeQuadModePass(*PR);
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2016-02-12 03:16:10 +01:00
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initializeSILowerControlFlowPass(*PR);
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2012-12-11 22:25:42 +01:00
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}
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2015-09-25 23:41:28 +02:00
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static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
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2015-12-10 03:13:01 +01:00
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return make_unique<AMDGPUTargetObjectFile>();
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2015-09-25 23:41:28 +02:00
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}
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2013-03-05 19:41:32 +01:00
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static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
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2014-04-21 22:32:32 +02:00
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return new ScheduleDAGMILive(C, make_unique<R600SchedStrategy>());
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2013-03-05 19:41:32 +01:00
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}
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static MachineSchedRegistry
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2016-01-13 17:10:10 +01:00
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R600SchedRegistry("r600", "Run R600's custom scheduler",
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createR600MachineScheduler);
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static MachineSchedRegistry
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SISchedRegistry("si", "Run SI's custom scheduler",
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createSIMachineScheduler);
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2013-03-05 19:41:32 +01:00
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2015-06-11 17:34:59 +02:00
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static std::string computeDataLayout(const Triple &TT) {
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2015-01-28 17:04:26 +01:00
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std::string Ret = "e-p:32:32";
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2015-06-11 17:34:59 +02:00
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if (TT.getArch() == Triple::amdgcn) {
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2015-01-28 17:04:26 +01:00
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// 32-bit private, local, and region pointers. 64-bit global and constant.
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Ret += "-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64";
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}
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Ret += "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256"
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"-v512:512-v1024:1024-v2048:2048-n32:64";
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return Ret;
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}
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2016-01-27 03:17:49 +01:00
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LLVM_READNONE
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static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
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if (!GPU.empty())
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return GPU;
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// HSA only supports CI+, so change the default GPU to a CI for HSA.
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if (TT.getArch() == Triple::amdgcn)
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return (TT.getOS() == Triple::AMDHSA) ? "kaveri" : "tahiti";
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return "";
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}
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2016-05-19 00:04:49 +02:00
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static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
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if (!RM.hasValue())
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return Reloc::PIC_;
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return *RM;
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}
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2015-06-11 21:41:26 +02:00
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AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
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2014-07-26 00:22:39 +02:00
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StringRef CPU, StringRef FS,
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2016-05-19 00:04:49 +02:00
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TargetOptions Options,
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Optional<Reloc::Model> RM,
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2014-07-26 00:22:39 +02:00
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CodeModel::Model CM,
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CodeGenOpt::Level OptLevel)
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2016-05-19 00:04:49 +02:00
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: LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
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FS, Options, getEffectiveRelocModel(RM), CM, OptLevel),
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2016-01-27 03:17:49 +01:00
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TLOF(createTLOF(getTargetTriple())),
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2016-05-19 00:04:49 +02:00
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Subtarget(TT, getTargetCPU(), FS, *this), IntrinsicInfo() {
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2013-12-07 02:49:19 +01:00
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setRequiresStructuredCFG(true);
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2013-05-13 03:16:13 +02:00
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initAsmInfo();
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2012-12-11 22:25:42 +01:00
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}
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2015-09-25 23:41:28 +02:00
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AMDGPUTargetMachine::~AMDGPUTargetMachine() { }
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2012-12-11 22:25:42 +01:00
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2015-02-11 18:11:50 +01:00
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//===----------------------------------------------------------------------===//
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// R600 Target Machine (R600 -> Cayman)
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//===----------------------------------------------------------------------===//
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2015-06-11 21:41:26 +02:00
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R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
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2016-02-05 19:29:17 +01:00
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StringRef CPU, StringRef FS,
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2016-05-19 00:04:49 +02:00
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TargetOptions Options,
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Optional<Reloc::Model> RM,
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2015-06-11 21:41:26 +02:00
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CodeModel::Model CM, CodeGenOpt::Level OL)
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2016-02-05 19:29:17 +01:00
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: AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
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2015-02-11 18:11:50 +01:00
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//===----------------------------------------------------------------------===//
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// GCN Target Machine (SI+)
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//===----------------------------------------------------------------------===//
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2015-06-11 21:41:26 +02:00
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GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
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2016-02-05 19:29:17 +01:00
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StringRef CPU, StringRef FS,
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2016-05-19 00:04:49 +02:00
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TargetOptions Options,
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Optional<Reloc::Model> RM,
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2015-06-11 21:41:26 +02:00
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CodeModel::Model CM, CodeGenOpt::Level OL)
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2016-02-05 19:29:17 +01:00
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: AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
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2015-02-11 18:11:50 +01:00
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//===----------------------------------------------------------------------===//
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// AMDGPU Pass Setup
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//===----------------------------------------------------------------------===//
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2012-12-11 22:25:42 +01:00
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namespace {
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2016-03-03 04:53:29 +01:00
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2012-12-11 22:25:42 +01:00
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class AMDGPUPassConfig : public TargetPassConfig {
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public:
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2015-02-11 18:11:51 +01:00
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AMDGPUPassConfig(TargetMachine *TM, PassManagerBase &PM)
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2015-09-25 19:41:20 +02:00
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: TargetPassConfig(TM, PM) {
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// Exceptions and StackMaps are not supported, so these passes will never do
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// anything.
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disablePass(&StackMapLivenessID);
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disablePass(&FuncletLayoutID);
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}
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2012-12-11 22:25:42 +01:00
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AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
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return getTM<AMDGPUTargetMachine>();
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}
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2013-09-20 07:14:41 +02:00
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2014-04-29 09:57:24 +02:00
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ScheduleDAGInstrs *
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createMachineScheduler(MachineSchedContext *C) const override {
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2015-03-21 04:17:25 +01:00
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const AMDGPUSubtarget &ST = *getAMDGPUTargetMachine().getSubtargetImpl();
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2013-09-20 07:14:41 +02:00
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if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
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return createR600MachineScheduler(C);
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2016-01-21 05:28:34 +01:00
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else if (ST.enableSIScheduler())
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return createSIMachineScheduler(C);
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2014-04-25 07:30:21 +02:00
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return nullptr;
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2013-09-20 07:14:41 +02:00
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}
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2014-11-03 20:49:05 +01:00
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void addIRPasses() override;
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2014-09-03 13:41:21 +02:00
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void addCodeGenPrepare() override;
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2015-09-25 19:41:20 +02:00
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bool addPreISel() override;
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bool addInstSelector() override;
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bool addGCPasses() override;
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2015-02-11 18:11:51 +01:00
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};
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2016-03-11 09:00:27 +01:00
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class R600PassConfig final : public AMDGPUPassConfig {
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2015-02-11 18:11:51 +01:00
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public:
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R600PassConfig(TargetMachine *TM, PassManagerBase &PM)
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: AMDGPUPassConfig(TM, PM) { }
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bool addPreISel() override;
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void addPreRegAlloc() override;
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void addPreSched2() override;
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void addPreEmitPass() override;
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};
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2016-03-11 09:00:27 +01:00
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class GCNPassConfig final : public AMDGPUPassConfig {
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2015-02-11 18:11:51 +01:00
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public:
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GCNPassConfig(TargetMachine *TM, PassManagerBase &PM)
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: AMDGPUPassConfig(TM, PM) { }
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2014-04-29 09:57:24 +02:00
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bool addPreISel() override;
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2016-04-14 23:58:24 +02:00
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void addMachineSSAOptimization() override;
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2014-04-29 09:57:24 +02:00
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bool addInstSelector() override;
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2016-04-14 21:09:28 +02:00
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#ifdef LLVM_BUILD_GLOBAL_ISEL
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bool addIRTranslator() override;
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bool addRegBankSelect() override;
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#endif
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2015-10-02 00:10:03 +02:00
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void addFastRegAlloc(FunctionPass *RegAllocPass) override;
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void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
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2014-12-11 22:26:47 +01:00
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void addPreRegAlloc() override;
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void addPreSched2() override;
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void addPreEmitPass() override;
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2012-12-11 22:25:42 +01:00
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};
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2015-02-11 18:11:51 +01:00
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} // End of anonymous namespace
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2012-12-11 22:25:42 +01:00
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2015-02-01 14:20:00 +01:00
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TargetIRAnalysis AMDGPUTargetMachine::getTargetIRAnalysis() {
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2015-09-17 01:38:13 +02:00
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return TargetIRAnalysis([this](const Function &F) {
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2015-07-09 04:08:42 +02:00
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return TargetTransformInfo(
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AMDGPUTTIImpl(this, F.getParent()->getDataLayout()));
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});
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2013-07-27 02:01:07 +02:00
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}
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2014-11-03 20:49:05 +01:00
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void AMDGPUPassConfig::addIRPasses() {
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2016-05-18 17:41:07 +02:00
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// There is no reason to run these.
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disablePass(&StackMapLivenessID);
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disablePass(&FuncletLayoutID);
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disablePass(&PatchableFunctionID);
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2014-11-03 20:49:05 +01:00
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// Function calls are not supported, so make sure we inline everything.
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addPass(createAMDGPUAlwaysInlinePass());
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addPass(createAlwaysInlinerPass());
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// We need to add the barrier noop pass, otherwise adding the function
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// inlining pass will cause all of the PassConfigs passes to be run
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// one function at a time, which means if we have a nodule with two
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// functions, then we will generate code for the first function
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// without ever running any passes on the second.
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addPass(createBarrierNoopPass());
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2015-11-06 19:01:57 +01:00
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2015-08-08 01:19:30 +02:00
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// Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
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addPass(createAMDGPUOpenCLImageTypeLoweringPass());
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2015-11-06 19:01:57 +01:00
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2014-11-03 20:49:05 +01:00
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TargetPassConfig::addIRPasses();
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}
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2014-06-17 18:53:14 +02:00
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void AMDGPUPassConfig::addCodeGenPrepare() {
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2016-01-30 06:19:45 +01:00
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const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
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const AMDGPUSubtarget &ST = *TM.getSubtargetImpl();
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2016-02-02 20:32:42 +01:00
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if (TM.getOptLevel() > CodeGenOpt::None && ST.isPromoteAllocaEnabled()) {
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2016-01-30 06:19:45 +01:00
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addPass(createAMDGPUPromoteAlloca(&TM));
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2014-07-13 04:08:26 +02:00
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addPass(createSROAPass());
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}
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2014-06-17 18:53:14 +02:00
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TargetPassConfig::addCodeGenPrepare();
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}
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2012-12-11 22:25:42 +01:00
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bool
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AMDGPUPassConfig::addPreISel() {
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2013-08-06 04:43:45 +02:00
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addPass(createFlattenCFGPass());
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2012-12-11 22:25:42 +01:00
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return false;
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}
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bool AMDGPUPassConfig::addInstSelector() {
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addPass(createAMDGPUISelDag(getAMDGPUTargetMachine()));
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2015-02-11 18:11:51 +01:00
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return false;
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}
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2014-11-18 22:06:58 +01:00
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2015-09-25 19:41:20 +02:00
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bool AMDGPUPassConfig::addGCPasses() {
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// Do nothing. GC is not supported.
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return false;
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}
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2015-02-11 18:11:51 +01:00
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//===----------------------------------------------------------------------===//
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// R600 Pass Setup
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//===----------------------------------------------------------------------===//
|
2014-11-18 22:06:58 +01:00
|
|
|
|
2015-02-11 18:11:51 +01:00
|
|
|
bool R600PassConfig::addPreISel() {
|
|
|
|
AMDGPUPassConfig::addPreISel();
|
2016-02-13 00:45:29 +01:00
|
|
|
const AMDGPUSubtarget &ST = *getAMDGPUTargetMachine().getSubtargetImpl();
|
|
|
|
if (ST.IsIRStructurizerEnabled())
|
|
|
|
addPass(createStructurizeCFGPass());
|
2015-02-11 18:11:51 +01:00
|
|
|
addPass(createR600TextureIntrinsicsReplacer());
|
2012-12-11 22:25:42 +01:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2015-02-11 18:11:51 +01:00
|
|
|
void R600PassConfig::addPreRegAlloc() {
|
|
|
|
addPass(createR600VectorRegMerger(*TM));
|
2012-12-11 22:25:42 +01:00
|
|
|
}
|
|
|
|
|
2015-02-11 18:11:51 +01:00
|
|
|
void R600PassConfig::addPreSched2() {
|
2015-03-21 04:17:25 +01:00
|
|
|
const AMDGPUSubtarget &ST = *getAMDGPUTargetMachine().getSubtargetImpl();
|
2015-02-11 18:11:51 +01:00
|
|
|
addPass(createR600EmitClauseMarkers(), false);
|
|
|
|
if (ST.isIfCvtEnabled())
|
|
|
|
addPass(&IfConverterID, false);
|
|
|
|
addPass(createR600ClauseMergePass(*TM), false);
|
|
|
|
}
|
2013-01-18 22:15:53 +01:00
|
|
|
|
2015-02-11 18:11:51 +01:00
|
|
|
void R600PassConfig::addPreEmitPass() {
|
|
|
|
addPass(createAMDGPUCFGStructurizerPass(), false);
|
|
|
|
addPass(createR600ExpandSpecialInstrsPass(*TM), false);
|
|
|
|
addPass(&FinalizeMachineBundlesID, false);
|
|
|
|
addPass(createR600Packetizer(*TM), false);
|
|
|
|
addPass(createR600ControlFlowFinalizer(*TM), false);
|
2012-12-11 22:25:42 +01:00
|
|
|
}
|
|
|
|
|
2015-02-11 18:11:51 +01:00
|
|
|
TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
|
|
|
|
return new R600PassConfig(this, PM);
|
|
|
|
}
|
2012-12-11 22:25:42 +01:00
|
|
|
|
2015-02-11 18:11:51 +01:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// GCN Pass Setup
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
bool GCNPassConfig::addPreISel() {
|
|
|
|
AMDGPUPassConfig::addPreISel();
|
2015-11-06 19:01:57 +01:00
|
|
|
|
|
|
|
// FIXME: We need to run a pass to propagate the attributes when calls are
|
|
|
|
// supported.
|
|
|
|
addPass(&AMDGPUAnnotateKernelFeaturesID);
|
2016-02-13 00:45:29 +01:00
|
|
|
addPass(createStructurizeCFGPass(true)); // true -> SkipUniformRegions
|
2015-02-11 18:11:51 +01:00
|
|
|
addPass(createSinkingPass());
|
|
|
|
addPass(createSITypeRewriter());
|
2015-12-15 21:55:55 +01:00
|
|
|
addPass(createAMDGPUAnnotateUniformValues());
|
2016-02-13 00:45:29 +01:00
|
|
|
addPass(createSIAnnotateControlFlowPass());
|
2015-12-15 21:55:55 +01:00
|
|
|
|
2015-02-11 18:11:51 +01:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2016-04-14 23:58:24 +02:00
|
|
|
void GCNPassConfig::addMachineSSAOptimization() {
|
|
|
|
TargetPassConfig::addMachineSSAOptimization();
|
|
|
|
|
|
|
|
// We want to fold operands after PeepholeOptimizer has run (or as part of
|
|
|
|
// it), because it will eliminate extra copies making it easier to fold the
|
|
|
|
// real source operand. We want to eliminate dead instructions after, so that
|
|
|
|
// we see fewer uses of the copies. We then need to clean up the dead
|
|
|
|
// instructions leftover after the operands are folded as well.
|
|
|
|
//
|
|
|
|
// XXX - Can we get away without running DeadMachineInstructionElim again?
|
|
|
|
addPass(&SIFoldOperandsID);
|
|
|
|
addPass(&DeadMachineInstructionElimID);
|
|
|
|
}
|
|
|
|
|
2015-02-11 18:11:51 +01:00
|
|
|
bool GCNPassConfig::addInstSelector() {
|
|
|
|
AMDGPUPassConfig::addInstSelector();
|
|
|
|
addPass(createSILowerI1CopiesPass());
|
2015-11-03 23:30:13 +01:00
|
|
|
addPass(&SIFixSGPRCopiesID);
|
2015-02-11 18:11:51 +01:00
|
|
|
return false;
|
2012-12-11 22:25:42 +01:00
|
|
|
}
|
|
|
|
|
2016-04-14 21:09:28 +02:00
|
|
|
#ifdef LLVM_BUILD_GLOBAL_ISEL
|
|
|
|
bool GCNPassConfig::addIRTranslator() {
|
|
|
|
addPass(new IRTranslator());
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool GCNPassConfig::addRegBankSelect() {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2015-02-11 18:11:51 +01:00
|
|
|
void GCNPassConfig::addPreRegAlloc() {
|
2015-03-21 04:17:25 +01:00
|
|
|
const AMDGPUSubtarget &ST = *getAMDGPUTargetMachine().getSubtargetImpl();
|
2015-05-12 19:13:02 +02:00
|
|
|
|
|
|
|
// This needs to be run directly before register allocation because
|
|
|
|
// earlier passes might recompute live intervals.
|
|
|
|
// TODO: handle CodeGenOpt::None; fast RA ignores spill weights set by the pass
|
|
|
|
if (getOptLevel() > CodeGenOpt::None) {
|
|
|
|
insertPass(&MachineSchedulerID, &SIFixControlFlowLiveIntervalsID);
|
|
|
|
}
|
|
|
|
|
2015-02-11 18:11:51 +01:00
|
|
|
if (getOptLevel() > CodeGenOpt::None && ST.loadStoreOptEnabled()) {
|
2015-03-21 04:17:25 +01:00
|
|
|
// Don't do this with no optimizations since it throws away debug info by
|
|
|
|
// merging nonadjacent loads.
|
2015-02-11 18:11:51 +01:00
|
|
|
|
2015-03-21 04:17:25 +01:00
|
|
|
// This should be run after scheduling, but before register allocation. It
|
|
|
|
// also need extra copies to the address operand to be eliminated.
|
|
|
|
insertPass(&MachineSchedulerID, &SILoadStoreOptimizerID);
|
2015-07-14 19:57:36 +02:00
|
|
|
insertPass(&MachineSchedulerID, &RegisterCoalescerID);
|
2012-12-11 22:25:42 +01:00
|
|
|
}
|
2015-02-11 18:11:51 +01:00
|
|
|
addPass(createSIShrinkInstructionsPass(), false);
|
2016-03-21 21:28:33 +01:00
|
|
|
addPass(createSIWholeQuadModePass());
|
2015-10-02 00:10:03 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void GCNPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
|
|
|
|
TargetPassConfig::addFastRegAlloc(RegAllocPass);
|
|
|
|
}
|
|
|
|
|
|
|
|
void GCNPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
|
|
|
|
TargetPassConfig::addOptimizedRegAlloc(RegAllocPass);
|
2015-02-11 18:11:51 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
void GCNPassConfig::addPreSched2() {
|
|
|
|
}
|
|
|
|
|
|
|
|
void GCNPassConfig::addPreEmitPass() {
|
2016-04-30 02:23:06 +02:00
|
|
|
|
|
|
|
// The hazard recognizer that runs as part of the post-ra scheduler does not
|
|
|
|
// gaurantee to be able handle all hazards correctly. This is because
|
|
|
|
// if there are multiple scheduling regions in a basic block, the regions
|
|
|
|
// are scheduled bottom up, so when we begin to schedule a region we don't
|
|
|
|
// know what instructions were emitted directly before it.
|
|
|
|
//
|
|
|
|
// Here we add a stand-alone hazard recognizer pass which can handle all cases.
|
|
|
|
// hazard recognizer pass.
|
|
|
|
addPass(&PostRAHazardRecognizerID);
|
|
|
|
|
2016-02-05 18:42:38 +01:00
|
|
|
addPass(createSIInsertWaitsPass(), false);
|
2016-04-29 22:23:42 +02:00
|
|
|
addPass(createSIShrinkInstructionsPass());
|
2016-02-12 03:16:10 +01:00
|
|
|
addPass(createSILowerControlFlowPass(), false);
|
2016-05-10 20:33:41 +02:00
|
|
|
addPass(createSIDebuggerInsertNopsPass(), false);
|
2015-02-11 18:11:51 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
|
|
|
|
return new GCNPassConfig(this, PM);
|
2012-12-11 22:25:42 +01:00
|
|
|
}
|