2015-11-06 19:17:45 +01:00
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//=====-- AMDGPUSubtarget.h - Define Subtarget for AMDGPU ------*- C++ -*-====//
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2012-12-11 22:25:42 +01:00
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//==-----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief AMDGPU specific subclass of TargetSubtarget.
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//
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//===----------------------------------------------------------------------===//
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2015-11-06 19:17:45 +01:00
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#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H
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#define LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H
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2015-11-06 19:23:00 +01:00
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2013-06-07 22:37:48 +02:00
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#include "AMDGPU.h"
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2016-06-24 08:30:11 +02:00
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#include "R600InstrInfo.h"
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#include "R600ISelLowering.h"
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#include "R600FrameLowering.h"
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#include "SIInstrInfo.h"
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#include "SIISelLowering.h"
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#include "SIFrameLowering.h"
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2015-06-26 23:15:07 +02:00
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#include "Utils/AMDGPUBaseInfo.h"
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2016-04-14 21:09:28 +02:00
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#include "llvm/CodeGen/GlobalISel/GISelAccessor.h"
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2012-12-11 22:25:42 +01:00
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#include "llvm/Target/TargetSubtargetInfo.h"
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#define GET_SUBTARGETINFO_HEADER
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#include "AMDGPUGenSubtargetInfo.inc"
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namespace llvm {
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2015-01-20 20:33:04 +01:00
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class SIMachineFunctionInfo;
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2016-06-24 08:30:11 +02:00
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class StringRef;
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2015-01-20 20:33:04 +01:00
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2012-12-11 22:25:42 +01:00
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class AMDGPUSubtarget : public AMDGPUGenSubtargetInfo {
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2013-06-07 22:37:48 +02:00
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public:
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enum Generation {
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R600 = 0,
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R700,
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EVERGREEN,
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NORTHERN_ISLANDS,
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2013-10-29 17:37:28 +01:00
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SOUTHERN_ISLANDS,
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2014-12-07 13:18:57 +01:00
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SEA_ISLANDS,
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VOLCANIC_ISLANDS,
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2013-06-07 22:37:48 +02:00
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};
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2015-06-26 23:15:07 +02:00
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enum {
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ISAVersion0_0_0,
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ISAVersion7_0_0,
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ISAVersion7_0_1,
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ISAVersion8_0_0,
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2016-01-13 21:39:25 +01:00
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ISAVersion8_0_1,
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ISAVersion8_0_3
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2015-06-26 23:15:07 +02:00
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};
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2016-06-24 08:30:11 +02:00
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protected:
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// Basic subtarget description.
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Triple TargetTriple;
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2014-06-27 19:57:00 +02:00
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Generation Gen;
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2016-06-24 08:30:11 +02:00
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unsigned IsaVersion;
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unsigned WavefrontSize;
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int LocalMemorySize;
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int LDSBankCount;
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unsigned MaxPrivateElementSize;
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// Possibly statically set by tablegen, but may want to be overridden.
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2015-01-29 20:34:25 +01:00
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bool FastFMAF32;
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2016-01-18 22:13:50 +01:00
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bool HalfRate64Ops;
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2016-06-24 08:30:11 +02:00
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// Dynamially set bits that enable features.
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bool FP32Denormals;
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bool FP64Denormals;
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bool FPExceptions;
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2015-12-22 21:55:23 +01:00
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bool FlatForGlobal;
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2016-07-02 01:03:44 +02:00
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bool UnalignedBufferAccess;
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2016-06-24 08:30:11 +02:00
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bool EnableXNACK;
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bool DebuggerInsertNops;
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bool DebuggerReserveRegs;
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2016-06-25 05:11:28 +02:00
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bool DebuggerEmitPrologue;
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2016-06-24 08:30:11 +02:00
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// Used as options.
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bool EnableVGPRSpilling;
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2014-07-13 04:08:26 +02:00
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bool EnablePromoteAlloca;
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2014-10-11 00:01:59 +02:00
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bool EnableLoadStoreOpt;
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2015-07-06 18:01:58 +02:00
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bool EnableUnsafeDSOffsetFolding;
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2016-06-24 08:30:11 +02:00
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bool EnableSIScheduler;
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bool DumpCode;
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// Subtarget statically properties set by tablegen
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bool FP64;
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2015-04-08 03:09:26 +02:00
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bool IsGCN;
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bool GCN1Encoding;
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bool GCN3Encoding;
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2015-04-23 21:33:54 +02:00
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bool CIInsts;
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2016-06-24 08:30:11 +02:00
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bool SGPRInitBug;
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2016-02-27 09:53:55 +01:00
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bool HasSMemRealTime;
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bool Has16BitInsts;
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2016-06-24 08:30:11 +02:00
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bool FlatAddressSpace;
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bool R600ALUInst;
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bool CaymanISA;
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bool CFALUBug;
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bool HasVertexCache;
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short TexVTXClauseSize;
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// Dummy feature to use for assembler in tablegen.
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2015-04-23 21:33:54 +02:00
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bool FeatureDisable;
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2012-12-11 22:25:42 +01:00
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InstrItineraryData InstrItins;
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public:
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2016-06-24 08:30:11 +02:00
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AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
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const TargetMachine &TM);
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virtual ~AMDGPUSubtarget();
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2015-06-10 14:11:26 +02:00
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AMDGPUSubtarget &initializeSubtargetDependencies(const Triple &TT,
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StringRef GPU, StringRef FS);
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2014-06-27 19:57:00 +02:00
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2016-07-22 19:01:25 +02:00
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const AMDGPUInstrInfo *getInstrInfo() const override = 0;
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const AMDGPUFrameLowering *getFrameLowering() const override = 0;
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const AMDGPUTargetLowering *getTargetLowering() const override = 0;
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const AMDGPURegisterInfo *getRegisterInfo() const override = 0;
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2016-04-14 21:09:28 +02:00
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2014-08-04 23:25:23 +02:00
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const InstrItineraryData *getInstrItineraryData() const override {
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return &InstrItins;
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}
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2014-06-27 19:57:00 +02:00
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2014-04-30 07:53:27 +02:00
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void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
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2012-12-11 22:25:42 +01:00
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2016-06-24 08:30:11 +02:00
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bool isAmdHsaOS() const {
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return TargetTriple.getOS() == Triple::AMDHSA;
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2014-06-27 19:57:00 +02:00
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}
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Generation getGeneration() const {
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return Gen;
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}
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2016-06-24 08:30:11 +02:00
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unsigned getWavefrontSize() const {
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return WavefrontSize;
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2014-06-27 19:57:00 +02:00
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}
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2016-06-24 08:30:11 +02:00
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int getLocalMemorySize() const {
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return LocalMemorySize;
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2014-06-27 19:57:00 +02:00
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}
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2014-03-17 19:58:11 +01:00
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2016-06-24 08:30:11 +02:00
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int getLDSBankCount() const {
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return LDSBankCount;
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2014-07-15 01:40:49 +02:00
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}
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2016-06-24 08:30:11 +02:00
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unsigned getMaxPrivateElementSize() const {
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return MaxPrivateElementSize;
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2014-07-15 01:40:49 +02:00
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}
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2016-06-24 08:30:11 +02:00
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bool hasHWFP64() const {
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return FP64;
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2016-01-28 21:53:42 +01:00
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}
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2015-01-29 20:34:25 +01:00
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bool hasFastFMAF32() const {
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return FastFMAF32;
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}
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2016-01-18 22:13:50 +01:00
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bool hasHalfRate64Ops() const {
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return HalfRate64Ops;
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}
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2016-06-10 01:42:48 +02:00
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bool hasAddr64() const {
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return (getGeneration() < VOLCANIC_ISLANDS);
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}
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2014-03-17 19:58:11 +01:00
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bool hasBFE() const {
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return (getGeneration() >= EVERGREEN);
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}
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2014-06-10 21:00:20 +02:00
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bool hasBFI() const {
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return (getGeneration() >= EVERGREEN);
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}
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2014-03-17 19:58:11 +01:00
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bool hasBFM() const {
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return hasBFE();
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}
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2014-06-10 21:18:28 +02:00
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bool hasBCNT(unsigned Size) const {
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if (Size == 32)
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return (getGeneration() >= EVERGREEN);
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2014-07-18 08:07:13 +02:00
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if (Size == 64)
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return (getGeneration() >= SOUTHERN_ISLANDS);
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return false;
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2014-06-10 21:18:28 +02:00
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}
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2014-04-07 21:45:41 +02:00
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bool hasMulU24() const {
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return (getGeneration() >= EVERGREEN);
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}
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bool hasMulI24() const {
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return (getGeneration() >= SOUTHERN_ISLANDS ||
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hasCaymanISA());
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}
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2014-07-15 17:51:09 +02:00
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bool hasFFBL() const {
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return (getGeneration() >= EVERGREEN);
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}
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bool hasFFBH() const {
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return (getGeneration() >= EVERGREEN);
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}
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2015-04-30 19:15:56 +02:00
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bool hasCARRY() const {
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return (getGeneration() >= EVERGREEN);
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}
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bool hasBORROW() const {
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return (getGeneration() >= EVERGREEN);
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}
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2016-06-24 08:30:11 +02:00
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bool hasCaymanISA() const {
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return CaymanISA;
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}
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2014-07-13 04:08:26 +02:00
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bool isPromoteAllocaEnabled() const {
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return EnablePromoteAlloca;
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}
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2015-07-06 18:01:58 +02:00
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bool unsafeDSOffsetFoldingEnabled() const {
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return EnableUnsafeDSOffsetFolding;
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}
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2016-06-24 08:30:11 +02:00
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bool dumpCode() const {
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return DumpCode;
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2014-06-27 19:57:00 +02:00
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}
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2016-05-16 23:19:59 +02:00
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/// Return the amount of LDS that can be used that will not restrict the
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/// occupancy lower than WaveCount.
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unsigned getMaxLocalMemSizeWithWaveCount(unsigned WaveCount) const;
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/// Inverse of getMaxLocalMemWithWaveCount. Return the maximum wavecount if
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/// the given LDS memory size is the only constraint.
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unsigned getOccupancyWithLocalMemSize(uint32_t Bytes) const;
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2016-06-24 08:30:11 +02:00
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bool hasFP32Denormals() const {
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return FP32Denormals;
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2014-06-27 19:57:00 +02:00
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}
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2012-12-11 22:25:42 +01:00
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2016-06-24 08:30:11 +02:00
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bool hasFP64Denormals() const {
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return FP64Denormals;
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2016-02-12 03:40:47 +01:00
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}
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2016-06-24 08:30:11 +02:00
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bool hasFPExceptions() const {
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return FPExceptions;
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2015-03-09 16:48:09 +01:00
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}
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2016-06-24 08:30:11 +02:00
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bool useFlatForGlobal() const {
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return FlatForGlobal;
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2015-05-25 18:15:54 +02:00
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}
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2016-07-02 01:03:44 +02:00
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bool hasUnalignedBufferAccess() const {
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return UnalignedBufferAccess;
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}
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2016-06-24 08:30:11 +02:00
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bool isXNACKEnabled() const {
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return EnableXNACK;
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}
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2014-12-02 23:00:07 +01:00
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2016-06-24 08:30:11 +02:00
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unsigned getMaxWavesPerCU() const {
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if (getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
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return 10;
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// FIXME: Not sure what this is for other subtagets.
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return 8;
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}
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/// \brief Returns the offset in bytes from the start of the input buffer
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/// of the first explicit kernel argument.
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unsigned getExplicitKernelArgOffset() const {
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return isAmdHsaOS() ? 0 : 36;
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}
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unsigned getStackAlignment() const {
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// Scratch is allocated in 256 dword per wave blocks.
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return 4 * 256 / getWavefrontSize();
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}
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2015-06-26 23:15:07 +02:00
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2014-04-29 09:57:24 +02:00
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bool enableMachineScheduler() const override {
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2015-01-29 17:55:25 +01:00
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return true;
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2013-09-20 07:14:41 +02:00
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}
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2016-06-24 08:30:11 +02:00
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bool enableSubRegLiveness() const override {
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return true;
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}
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};
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2015-01-29 17:55:25 +01:00
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2016-06-24 08:30:11 +02:00
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class R600Subtarget final : public AMDGPUSubtarget {
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private:
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R600InstrInfo InstrInfo;
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R600FrameLowering FrameLowering;
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R600TargetLowering TLInfo;
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public:
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R600Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
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const TargetMachine &TM);
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const R600InstrInfo *getInstrInfo() const override {
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return &InstrInfo;
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2014-06-27 19:57:00 +02:00
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}
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2012-12-11 22:25:42 +01:00
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2016-06-24 08:30:11 +02:00
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const R600FrameLowering *getFrameLowering() const override {
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return &FrameLowering;
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2016-01-21 05:28:34 +01:00
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}
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2016-06-24 08:30:11 +02:00
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const R600TargetLowering *getTargetLowering() const override {
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return &TLInfo;
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2016-04-18 18:28:23 +02:00
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}
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2016-06-24 08:30:11 +02:00
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const R600RegisterInfo *getRegisterInfo() const override {
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return &InstrInfo.getRegisterInfo();
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2016-04-26 17:43:14 +02:00
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}
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2016-06-24 08:30:11 +02:00
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bool hasCFAluBug() const {
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return CFALUBug;
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2014-06-27 19:57:00 +02:00
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}
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2016-06-24 08:30:11 +02:00
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bool hasVertexCache() const {
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return HasVertexCache;
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2014-06-27 19:57:00 +02:00
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}
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2016-06-24 08:30:11 +02:00
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short getTexVTXClauseSize() const {
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return TexVTXClauseSize;
|
2014-12-02 18:05:41 +01:00
|
|
|
}
|
2016-06-24 08:30:11 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
class SISubtarget final : public AMDGPUSubtarget {
|
|
|
|
public:
|
|
|
|
enum {
|
2016-08-05 23:23:29 +02:00
|
|
|
// The closed Vulkan driver sets 96, which limits the wave count to 8 but
|
|
|
|
// doesn't spill SGPRs as much as when 80 is set.
|
|
|
|
FIXED_SGPR_COUNT_FOR_INIT_BUG = 96
|
2016-06-24 08:30:11 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
private:
|
|
|
|
SIInstrInfo InstrInfo;
|
|
|
|
SIFrameLowering FrameLowering;
|
|
|
|
SITargetLowering TLInfo;
|
|
|
|
std::unique_ptr<GISelAccessor> GISel;
|
|
|
|
|
|
|
|
public:
|
|
|
|
SISubtarget(const Triple &TT, StringRef CPU, StringRef FS,
|
|
|
|
const TargetMachine &TM);
|
|
|
|
|
|
|
|
const SIInstrInfo *getInstrInfo() const override {
|
|
|
|
return &InstrInfo;
|
2016-01-05 00:35:53 +01:00
|
|
|
}
|
|
|
|
|
2016-06-24 08:30:11 +02:00
|
|
|
const SIFrameLowering *getFrameLowering() const override {
|
|
|
|
return &FrameLowering;
|
|
|
|
}
|
2015-01-29 17:55:25 +01:00
|
|
|
|
2016-06-24 08:30:11 +02:00
|
|
|
const SITargetLowering *getTargetLowering() const override {
|
|
|
|
return &TLInfo;
|
2015-01-29 17:55:25 +01:00
|
|
|
}
|
2015-02-05 00:14:18 +01:00
|
|
|
|
2016-06-24 08:30:11 +02:00
|
|
|
const CallLowering *getCallLowering() const override {
|
|
|
|
assert(GISel && "Access to GlobalISel APIs not set");
|
|
|
|
return GISel->getCallLowering();
|
2015-02-05 00:14:18 +01:00
|
|
|
}
|
2015-06-26 23:15:03 +02:00
|
|
|
|
2016-06-24 08:30:11 +02:00
|
|
|
const SIRegisterInfo *getRegisterInfo() const override {
|
|
|
|
return &InstrInfo.getRegisterInfo();
|
2015-06-26 23:15:03 +02:00
|
|
|
}
|
|
|
|
|
2016-06-24 08:30:11 +02:00
|
|
|
void setGISelAccessor(GISelAccessor &GISel) {
|
|
|
|
this->GISel.reset(&GISel);
|
|
|
|
}
|
|
|
|
|
|
|
|
void overrideSchedPolicy(MachineSchedPolicy &Policy,
|
|
|
|
unsigned NumRegionInstrs) const override;
|
|
|
|
|
|
|
|
bool isVGPRSpillingEnabled(const Function& F) const;
|
|
|
|
|
2015-11-30 22:16:07 +01:00
|
|
|
unsigned getMaxNumUserSGPRs() const {
|
|
|
|
return 16;
|
|
|
|
}
|
2016-06-24 08:30:11 +02:00
|
|
|
|
|
|
|
bool hasFlatAddressSpace() const {
|
|
|
|
return FlatAddressSpace;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool hasSMemRealTime() const {
|
|
|
|
return HasSMemRealTime;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool has16BitInsts() const {
|
|
|
|
return Has16BitInsts;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool enableSIScheduler() const {
|
|
|
|
return EnableSIScheduler;
|
|
|
|
}
|
|
|
|
|
2016-06-25 05:11:28 +02:00
|
|
|
bool debuggerSupported() const {
|
|
|
|
return debuggerInsertNops() && debuggerReserveRegs() &&
|
|
|
|
debuggerEmitPrologue();
|
|
|
|
}
|
|
|
|
|
2016-06-24 08:30:11 +02:00
|
|
|
bool debuggerInsertNops() const {
|
|
|
|
return DebuggerInsertNops;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool debuggerReserveRegs() const {
|
|
|
|
return DebuggerReserveRegs;
|
|
|
|
}
|
|
|
|
|
2016-06-25 05:11:28 +02:00
|
|
|
bool debuggerEmitPrologue() const {
|
|
|
|
return DebuggerEmitPrologue;
|
|
|
|
}
|
|
|
|
|
2016-06-24 08:30:11 +02:00
|
|
|
bool loadStoreOptEnabled() const {
|
|
|
|
return EnableLoadStoreOpt;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool hasSGPRInitBug() const {
|
|
|
|
return SGPRInitBug;
|
|
|
|
}
|
2012-12-11 22:25:42 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
} // End namespace llvm
|
|
|
|
|
2014-08-13 18:26:38 +02:00
|
|
|
#endif
|