2018-03-08 14:05:02 +01:00
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//===-- llvm-mca.cpp - Machine Code Analyzer -------------------*- C++ -* -===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This utility is a simple driver that allows static performance analysis on
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// machine code similarly to how IACA (Intel Architecture Code Analyzer) works.
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//
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// llvm-mca [options] <file-name>
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// -march <type>
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// -mcpu <cpu>
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// -o <file>
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//
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// The target defaults to the host target.
|
2018-04-25 12:18:25 +02:00
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// The cpu defaults to the 'native' host cpu.
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2018-03-08 14:05:02 +01:00
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// The output defaults to standard output.
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//
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//===----------------------------------------------------------------------===//
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2018-04-09 18:39:52 +02:00
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#include "CodeRegion.h"
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2018-11-07 20:20:04 +01:00
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#include "CodeRegionGenerator.h"
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2018-06-25 18:53:00 +02:00
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#include "PipelinePrinter.h"
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2018-11-08 18:49:30 +01:00
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#include "Stages/EntryStage.h"
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[llvm-mca] Introduce the llvm-mca library and organize the directory accordingly. NFC.
Summary:
This patch introduces llvm-mca as a library. The driver (llvm-mca.cpp), views, and stats, are not part of the library.
Those are separate components that are not required for the functioning of llvm-mca.
The directory has been organized as follows:
All library source files now reside in:
- `lib/HardwareUnits/` - All subclasses of HardwareUnit (these represent the simulated hardware components of a backend).
(LSUnit does not inherit from HardwareUnit, but Scheduler does which uses LSUnit).
- `lib/Stages/` - All subclasses of the pipeline stages.
- `lib/` - This is the root of the library and contains library code that does not fit into the Stages or HardwareUnit subdirs.
All library header files now reside in the `include` directory and mimic the same layout as the `lib` directory mentioned above.
In the (near) future we would like to move the library (include and lib) contents from tools and into the core of llvm somewhere.
That change would allow various analysis and optimization passes to make use of MCA functionality for things like cost modeling.
I left all of the non-library code just where it has always been, in the root of the llvm-mca directory.
The include directives for the non-library source file have been updated to refer to the llvm-mca library headers.
I updated the llvm-mca/CMakeLists.txt file to include the library headers, but I made the non-library code
explicitly reference the library's 'include' directory. Once we eventually (hopefully) migrate the MCA library
components into llvm the include directives used by the non-library source files will be updated to point to the
proper location in llvm.
Reviewers: andreadb, courbet, RKSimon
Reviewed By: andreadb
Subscribers: mgorny, javed.absar, tschuett, gbedwell, llvm-commits
Differential Revision: https://reviews.llvm.org/D50929
llvm-svn: 340755
2018-08-27 19:16:32 +02:00
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#include "Stages/InstructionTables.h"
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2018-08-24 22:24:53 +02:00
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#include "Views/DispatchStatistics.h"
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#include "Views/InstructionInfoView.h"
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#include "Views/RegisterFileStatistics.h"
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#include "Views/ResourcePressureView.h"
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#include "Views/RetireControlUnitStatistics.h"
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#include "Views/SchedulerStatistics.h"
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#include "Views/SummaryView.h"
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#include "Views/TimelineView.h"
|
[llvm-mca] Introduce the llvm-mca library and organize the directory accordingly. NFC.
Summary:
This patch introduces llvm-mca as a library. The driver (llvm-mca.cpp), views, and stats, are not part of the library.
Those are separate components that are not required for the functioning of llvm-mca.
The directory has been organized as follows:
All library source files now reside in:
- `lib/HardwareUnits/` - All subclasses of HardwareUnit (these represent the simulated hardware components of a backend).
(LSUnit does not inherit from HardwareUnit, but Scheduler does which uses LSUnit).
- `lib/Stages/` - All subclasses of the pipeline stages.
- `lib/` - This is the root of the library and contains library code that does not fit into the Stages or HardwareUnit subdirs.
All library header files now reside in the `include` directory and mimic the same layout as the `lib` directory mentioned above.
In the (near) future we would like to move the library (include and lib) contents from tools and into the core of llvm somewhere.
That change would allow various analysis and optimization passes to make use of MCA functionality for things like cost modeling.
I left all of the non-library code just where it has always been, in the root of the llvm-mca directory.
The include directives for the non-library source file have been updated to refer to the llvm-mca library headers.
I updated the llvm-mca/CMakeLists.txt file to include the library headers, but I made the non-library code
explicitly reference the library's 'include' directory. Once we eventually (hopefully) migrate the MCA library
components into llvm the include directives used by the non-library source files will be updated to point to the
proper location in llvm.
Reviewers: andreadb, courbet, RKSimon
Reviewed By: andreadb
Subscribers: mgorny, javed.absar, tschuett, gbedwell, llvm-commits
Differential Revision: https://reviews.llvm.org/D50929
llvm-svn: 340755
2018-08-27 19:16:32 +02:00
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#include "include/Context.h"
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#include "include/Pipeline.h"
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2018-10-24 12:56:47 +02:00
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#include "include/Support.h"
|
2018-03-08 14:05:02 +01:00
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCObjectFileInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/Support/CommandLine.h"
|
2018-08-13 20:11:48 +02:00
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#include "llvm/Support/ErrorHandling.h"
|
2018-03-08 17:08:43 +01:00
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#include "llvm/Support/ErrorOr.h"
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#include "llvm/Support/FileSystem.h"
|
2018-04-25 12:27:30 +02:00
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#include "llvm/Support/Host.h"
|
2018-04-13 20:26:06 +02:00
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#include "llvm/Support/InitLLVM.h"
|
2018-03-08 14:05:02 +01:00
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#include "llvm/Support/MemoryBuffer.h"
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#include "llvm/Support/SourceMgr.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/TargetSelect.h"
|
2018-03-08 17:08:43 +01:00
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#include "llvm/Support/ToolOutputFile.h"
|
2018-04-18 17:26:51 +02:00
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#include "llvm/Support/WithColor.h"
|
2018-03-08 14:05:02 +01:00
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using namespace llvm;
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|
2018-05-17 17:35:14 +02:00
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static cl::OptionCategory ToolOptions("Tool Options");
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static cl::OptionCategory ViewOptions("View Options");
|
2018-04-25 13:33:14 +02:00
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|
2018-05-17 17:35:14 +02:00
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static cl::opt<std::string> InputFilename(cl::Positional,
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cl::desc("<input file>"),
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cl::cat(ToolOptions), cl::init("-"));
|
2018-03-08 14:05:02 +01:00
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static cl::opt<std::string> OutputFilename("o", cl::desc("Output filename"),
|
2018-05-17 17:35:14 +02:00
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cl::init("-"), cl::cat(ToolOptions),
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2018-03-08 14:05:02 +01:00
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|
cl::value_desc("filename"));
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static cl::opt<std::string>
|
2018-10-31 18:47:25 +01:00
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ArchName("march", cl::desc("Target architecture. "
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"See -version for available targets"),
|
2018-05-17 17:35:14 +02:00
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|
cl::cat(ToolOptions));
|
2018-03-08 14:05:02 +01:00
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static cl::opt<std::string>
|
2018-10-22 17:36:15 +02:00
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TripleName("mtriple",
|
2018-10-31 18:47:25 +01:00
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|
cl::desc("Target triple. See -version for available targets"),
|
2018-05-17 17:35:14 +02:00
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|
|
cl::cat(ToolOptions));
|
2018-03-08 14:05:02 +01:00
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static cl::opt<std::string>
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MCPU("mcpu",
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cl::desc("Target a specific cpu type (-mcpu=help for details)"),
|
2018-05-17 17:35:14 +02:00
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|
cl::value_desc("cpu-name"), cl::cat(ToolOptions), cl::init("native"));
|
2018-03-08 14:05:02 +01:00
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|
2018-04-24 18:19:08 +02:00
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|
static cl::opt<int>
|
2018-03-08 14:05:02 +01:00
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OutputAsmVariant("output-asm-variant",
|
2018-04-24 18:19:08 +02:00
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|
cl::desc("Syntax variant to use for output printing"),
|
2018-05-17 17:35:14 +02:00
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|
cl::cat(ToolOptions), cl::init(-1));
|
2018-03-08 14:05:02 +01:00
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static cl::opt<unsigned> Iterations("iterations",
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|
cl::desc("Number of iterations to run"),
|
2018-05-17 17:35:14 +02:00
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|
|
cl::cat(ToolOptions), cl::init(0));
|
2018-03-08 14:05:02 +01:00
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|
2018-05-17 17:35:14 +02:00
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|
static cl::opt<unsigned>
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|
DispatchWidth("dispatch", cl::desc("Override the processor dispatch width"),
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|
cl::cat(ToolOptions), cl::init(0));
|
2018-03-08 14:05:02 +01:00
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static cl::opt<unsigned>
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RegisterFileSize("register-file-size",
|
2018-07-31 22:05:08 +02:00
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|
cl::desc("Maximum number of physical registers which can "
|
2018-03-08 14:05:02 +01:00
|
|
|
"be used for register mappings"),
|
2018-05-17 17:35:14 +02:00
|
|
|
cl::cat(ToolOptions), cl::init(0));
|
2018-03-08 14:05:02 +01:00
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|
2018-04-03 18:46:23 +02:00
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|
static cl::opt<bool>
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PrintRegisterFileStats("register-file-stats",
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|
cl::desc("Print register file statistics"),
|
2018-05-05 17:36:47 +02:00
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|
|
cl::cat(ViewOptions), cl::init(false));
|
2018-04-03 18:46:23 +02:00
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|
2018-04-25 12:27:30 +02:00
|
|
|
static cl::opt<bool> PrintDispatchStats("dispatch-stats",
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|
|
cl::desc("Print dispatch statistics"),
|
2018-05-05 17:36:47 +02:00
|
|
|
cl::cat(ViewOptions), cl::init(false));
|
2018-04-10 16:55:14 +02:00
|
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|
2018-06-15 16:01:43 +02:00
|
|
|
static cl::opt<bool>
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|
|
PrintSummaryView("summary-view", cl::Hidden,
|
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|
|
cl::desc("Print summary view (enabled by default)"),
|
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|
|
cl::cat(ViewOptions), cl::init(true));
|
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|
|
2018-04-25 12:27:30 +02:00
|
|
|
static cl::opt<bool> PrintSchedulerStats("scheduler-stats",
|
|
|
|
cl::desc("Print scheduler statistics"),
|
2018-05-05 17:36:47 +02:00
|
|
|
cl::cat(ViewOptions), cl::init(false));
|
2018-04-11 13:37:46 +02:00
|
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|
2018-04-11 14:12:53 +02:00
|
|
|
static cl::opt<bool>
|
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|
|
PrintRetireStats("retire-stats",
|
2018-04-25 12:27:30 +02:00
|
|
|
cl::desc("Print retire control unit statistics"),
|
2018-05-05 17:36:47 +02:00
|
|
|
cl::cat(ViewOptions), cl::init(false));
|
2018-04-11 14:12:53 +02:00
|
|
|
|
2018-05-05 17:36:47 +02:00
|
|
|
static cl::opt<bool> PrintResourcePressureView(
|
|
|
|
"resource-pressure",
|
|
|
|
cl::desc("Print the resource pressure view (enabled by default)"),
|
|
|
|
cl::cat(ViewOptions), cl::init(true));
|
2018-03-23 12:33:09 +01:00
|
|
|
|
2018-03-08 14:05:02 +01:00
|
|
|
static cl::opt<bool> PrintTimelineView("timeline",
|
|
|
|
cl::desc("Print the timeline view"),
|
2018-05-05 17:36:47 +02:00
|
|
|
cl::cat(ViewOptions), cl::init(false));
|
2018-03-08 14:05:02 +01:00
|
|
|
|
|
|
|
static cl::opt<unsigned> TimelineMaxIterations(
|
|
|
|
"timeline-max-iterations",
|
|
|
|
cl::desc("Maximum number of iterations to print in timeline view"),
|
2018-05-05 17:36:47 +02:00
|
|
|
cl::cat(ViewOptions), cl::init(0));
|
2018-03-08 14:05:02 +01:00
|
|
|
|
|
|
|
static cl::opt<unsigned> TimelineMaxCycles(
|
|
|
|
"timeline-max-cycles",
|
|
|
|
cl::desc(
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|
|
|
"Maximum number of cycles in the timeline view. Defaults to 80 cycles"),
|
2018-05-05 17:36:47 +02:00
|
|
|
cl::cat(ViewOptions), cl::init(80));
|
2018-03-08 14:05:02 +01:00
|
|
|
|
2018-05-17 17:35:14 +02:00
|
|
|
static cl::opt<bool>
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|
|
AssumeNoAlias("noalias",
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|
|
cl::desc("If set, assume that loads and stores do not alias"),
|
|
|
|
cl::cat(ToolOptions), cl::init(true));
|
2018-03-08 14:05:02 +01:00
|
|
|
|
|
|
|
static cl::opt<unsigned>
|
2018-05-17 17:35:14 +02:00
|
|
|
LoadQueueSize("lqueue",
|
[llvm-mca][MC] Add the ability to declare which processor resources model load/store queues (PR36666).
This patch adds the ability to specify via tablegen which processor resources
are load/store queue resources.
A new tablegen class named MemoryQueue can be optionally used to mark resources
that model load/store queues. Information about the load/store queue is
collected at 'CodeGenSchedule' stage, and analyzed by the 'SubtargetEmitter' to
initialize two new fields in struct MCExtraProcessorInfo named `LoadQueueID` and
`StoreQueueID`. Those two fields are identifiers for buffered resources used to
describe the load queue and the store queue.
Field `BufferSize` is interpreted as the number of entries in the queue, while
the number of units is a throughput indicator (i.e. number of available pickers
for loads/stores).
At construction time, LSUnit in llvm-mca checks for the presence of extra
processor information (i.e. MCExtraProcessorInfo) in the scheduling model. If
that information is available, and fields LoadQueueID and StoreQueueID are set
to a value different than zero (i.e. the invalid processor resource index), then
LSUnit initializes its LoadQueue/StoreQueue based on the BufferSize value
declared by the two processor resources.
With this patch, we more accurately track dynamic dispatch stalls caused by the
lack of LS tokens (i.e. load/store queue full). This is also shown by the
differences in two BdVer2 tests. Stalls that were previously classified as
generic SCHEDULER FULL stalls, are not correctly classified either as "load
queue full" or "store queue full".
About the differences in the -scheduler-stats view: those differences are
expected, because entries in the load/store queue are not released at
instruction issue stage. Instead, those are released at instruction executed
stage. This is the main reason why for the modified tests, the load/store
queues gets full before PdEx is full.
Differential Revision: https://reviews.llvm.org/D54957
llvm-svn: 347857
2018-11-29 13:15:56 +01:00
|
|
|
cl::desc("Size of the load queue"),
|
2018-05-17 17:35:14 +02:00
|
|
|
cl::cat(ToolOptions), cl::init(0));
|
2018-03-26 14:04:53 +02:00
|
|
|
|
2018-03-08 14:05:02 +01:00
|
|
|
static cl::opt<unsigned>
|
2018-05-17 17:35:14 +02:00
|
|
|
StoreQueueSize("squeue",
|
[llvm-mca][MC] Add the ability to declare which processor resources model load/store queues (PR36666).
This patch adds the ability to specify via tablegen which processor resources
are load/store queue resources.
A new tablegen class named MemoryQueue can be optionally used to mark resources
that model load/store queues. Information about the load/store queue is
collected at 'CodeGenSchedule' stage, and analyzed by the 'SubtargetEmitter' to
initialize two new fields in struct MCExtraProcessorInfo named `LoadQueueID` and
`StoreQueueID`. Those two fields are identifiers for buffered resources used to
describe the load queue and the store queue.
Field `BufferSize` is interpreted as the number of entries in the queue, while
the number of units is a throughput indicator (i.e. number of available pickers
for loads/stores).
At construction time, LSUnit in llvm-mca checks for the presence of extra
processor information (i.e. MCExtraProcessorInfo) in the scheduling model. If
that information is available, and fields LoadQueueID and StoreQueueID are set
to a value different than zero (i.e. the invalid processor resource index), then
LSUnit initializes its LoadQueue/StoreQueue based on the BufferSize value
declared by the two processor resources.
With this patch, we more accurately track dynamic dispatch stalls caused by the
lack of LS tokens (i.e. load/store queue full). This is also shown by the
differences in two BdVer2 tests. Stalls that were previously classified as
generic SCHEDULER FULL stalls, are not correctly classified either as "load
queue full" or "store queue full".
About the differences in the -scheduler-stats view: those differences are
expected, because entries in the load/store queue are not released at
instruction issue stage. Instead, those are released at instruction executed
stage. This is the main reason why for the modified tests, the load/store
queues gets full before PdEx is full.
Differential Revision: https://reviews.llvm.org/D54957
llvm-svn: 347857
2018-11-29 13:15:56 +01:00
|
|
|
cl::desc("Size of the store queue"),
|
2018-05-17 17:35:14 +02:00
|
|
|
cl::cat(ToolOptions), cl::init(0));
|
2018-03-08 14:05:02 +01:00
|
|
|
|
2018-03-26 14:04:53 +02:00
|
|
|
static cl::opt<bool>
|
|
|
|
PrintInstructionTables("instruction-tables",
|
|
|
|
cl::desc("Print instruction tables"),
|
2018-05-17 17:35:14 +02:00
|
|
|
cl::cat(ToolOptions), cl::init(false));
|
2018-03-26 14:04:53 +02:00
|
|
|
|
2018-05-05 17:36:47 +02:00
|
|
|
static cl::opt<bool> PrintInstructionInfoView(
|
|
|
|
"instruction-info",
|
|
|
|
cl::desc("Print the instruction info view (enabled by default)"),
|
|
|
|
cl::cat(ViewOptions), cl::init(true));
|
2018-03-26 15:44:54 +02:00
|
|
|
|
2018-05-17 14:27:03 +02:00
|
|
|
static cl::opt<bool> EnableAllStats("all-stats",
|
|
|
|
cl::desc("Print all hardware statistics"),
|
|
|
|
cl::cat(ViewOptions), cl::init(false));
|
|
|
|
|
|
|
|
static cl::opt<bool>
|
|
|
|
EnableAllViews("all-views",
|
|
|
|
cl::desc("Print all views including hardware statistics"),
|
|
|
|
cl::cat(ViewOptions), cl::init(false));
|
|
|
|
|
2018-04-08 17:10:19 +02:00
|
|
|
namespace {
|
|
|
|
|
|
|
|
const Target *getTarget(const char *ProgName) {
|
2018-03-08 14:05:02 +01:00
|
|
|
if (TripleName.empty())
|
|
|
|
TripleName = Triple::normalize(sys::getDefaultTargetTriple());
|
|
|
|
Triple TheTriple(TripleName);
|
|
|
|
|
|
|
|
// Get the target specific parser.
|
|
|
|
std::string Error;
|
|
|
|
const Target *TheTarget =
|
|
|
|
TargetRegistry::lookupTarget(ArchName, TheTriple, Error);
|
|
|
|
if (!TheTarget) {
|
|
|
|
errs() << ProgName << ": " << Error;
|
|
|
|
return nullptr;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Return the found target.
|
|
|
|
return TheTarget;
|
|
|
|
}
|
|
|
|
|
2018-04-08 17:10:19 +02:00
|
|
|
ErrorOr<std::unique_ptr<ToolOutputFile>> getOutputStream() {
|
2018-03-08 17:08:43 +01:00
|
|
|
if (OutputFilename == "")
|
|
|
|
OutputFilename = "-";
|
|
|
|
std::error_code EC;
|
2018-11-08 19:08:43 +01:00
|
|
|
auto Out =
|
|
|
|
llvm::make_unique<ToolOutputFile>(OutputFilename, EC, sys::fs::F_None);
|
2018-03-08 17:08:43 +01:00
|
|
|
if (!EC)
|
|
|
|
return std::move(Out);
|
|
|
|
return EC;
|
|
|
|
}
|
2018-03-08 14:05:02 +01:00
|
|
|
} // end of anonymous namespace
|
|
|
|
|
2018-05-17 14:27:03 +02:00
|
|
|
static void processOptionImpl(cl::opt<bool> &O, const cl::opt<bool> &Default) {
|
|
|
|
if (!O.getNumOccurrences() || O.getPosition() < Default.getPosition())
|
|
|
|
O = Default.getValue();
|
|
|
|
}
|
|
|
|
|
|
|
|
static void processViewOptions() {
|
|
|
|
if (!EnableAllViews.getNumOccurrences() &&
|
|
|
|
!EnableAllStats.getNumOccurrences())
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (EnableAllViews.getNumOccurrences()) {
|
2018-06-15 16:01:43 +02:00
|
|
|
processOptionImpl(PrintSummaryView, EnableAllViews);
|
2018-05-17 14:27:03 +02:00
|
|
|
processOptionImpl(PrintResourcePressureView, EnableAllViews);
|
|
|
|
processOptionImpl(PrintTimelineView, EnableAllViews);
|
|
|
|
processOptionImpl(PrintInstructionInfoView, EnableAllViews);
|
|
|
|
}
|
|
|
|
|
|
|
|
const cl::opt<bool> &Default =
|
|
|
|
EnableAllViews.getPosition() < EnableAllStats.getPosition()
|
|
|
|
? EnableAllStats
|
|
|
|
: EnableAllViews;
|
|
|
|
processOptionImpl(PrintRegisterFileStats, Default);
|
|
|
|
processOptionImpl(PrintDispatchStats, Default);
|
|
|
|
processOptionImpl(PrintSchedulerStats, Default);
|
|
|
|
processOptionImpl(PrintRetireStats, Default);
|
|
|
|
}
|
|
|
|
|
2018-10-24 12:56:47 +02:00
|
|
|
// Returns true on success.
|
[llvm-mca] Lower to mca::Instructon before the pipeline is run.
Before this change, the lowering of instructions from llvm::MCInst to
mca::Instruction was done as part of the first stage of the pipeline (i.e. the
FetchStage). In particular, FetchStage was responsible for picking the next
instruction from the source sequence, and lower it to an mca::Instruction with
the help of an object of class InstrBuilder.
The dependency on InstrBuilder was problematic for a number of reasons. Class
InstrBuilder only knows how to lower from llvm::MCInst to mca::Instruction.
That means, it is hard to support a different scenario where instructions
in input are not instances of class llvm::MCInst. Even if we managed to
specialize InstrBuilder, and generalize most of its internal logic, the
dependency on InstrBuilder in FetchStage would have caused more troubles (other
than complicating the pipeline logic).
With this patch, the lowering step is done before the pipeline is run. The
pipeline is no longer responsible for lowering from MCInst to mca::Instruction.
As a consequence of this, the FetchStage no longer needs to interact with an
InstrBuilder. The mca::SourceMgr class now simply wraps a reference to a
sequence of mca::Instruction objects.
This simplifies the logic of FetchStage, and increases the usability of it. As
a result, on a debug build, we see a 7-9% speedup; on a release build, the
speedup is around 3-4%.
llvm-svn: 345500
2018-10-29 14:29:22 +01:00
|
|
|
static bool runPipeline(mca::Pipeline &P) {
|
2018-10-24 12:56:47 +02:00
|
|
|
// Handle pipeline errors here.
|
2018-11-28 20:31:19 +01:00
|
|
|
Expected<unsigned> Cycles = P.run();
|
|
|
|
if (!Cycles) {
|
|
|
|
WithColor::error() << toString(Cycles.takeError());
|
2018-10-24 12:56:47 +02:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2018-03-08 14:05:02 +01:00
|
|
|
int main(int argc, char **argv) {
|
2018-04-13 20:26:06 +02:00
|
|
|
InitLLVM X(argc, argv);
|
2018-03-08 14:05:02 +01:00
|
|
|
|
|
|
|
// Initialize targets and assembly parsers.
|
2018-11-08 18:32:45 +01:00
|
|
|
InitializeAllTargetInfos();
|
|
|
|
InitializeAllTargetMCs();
|
|
|
|
InitializeAllAsmParsers();
|
2018-03-08 14:05:02 +01:00
|
|
|
|
|
|
|
// Enable printing of available targets when flag --version is specified.
|
|
|
|
cl::AddExtraVersionPrinter(TargetRegistry::printRegisteredTargetsForVersion);
|
|
|
|
|
2018-05-17 17:35:14 +02:00
|
|
|
cl::HideUnrelatedOptions({&ToolOptions, &ViewOptions});
|
|
|
|
|
2018-03-08 14:05:02 +01:00
|
|
|
// Parse flags and initialize target options.
|
|
|
|
cl::ParseCommandLineOptions(argc, argv,
|
|
|
|
"llvm machine code performance analyzer.\n");
|
2018-05-17 17:35:14 +02:00
|
|
|
|
2018-03-08 14:05:02 +01:00
|
|
|
// Get the target from the triple. If a triple is not specified, then select
|
|
|
|
// the default triple for the host. If the triple doesn't correspond to any
|
|
|
|
// registered target, then exit with an error message.
|
|
|
|
const char *ProgName = argv[0];
|
|
|
|
const Target *TheTarget = getTarget(ProgName);
|
|
|
|
if (!TheTarget)
|
|
|
|
return 1;
|
|
|
|
|
|
|
|
// GetTarget() may replaced TripleName with a default triple.
|
|
|
|
// For safety, reconstruct the Triple object.
|
|
|
|
Triple TheTriple(TripleName);
|
|
|
|
|
|
|
|
ErrorOr<std::unique_ptr<MemoryBuffer>> BufferPtr =
|
|
|
|
MemoryBuffer::getFileOrSTDIN(InputFilename);
|
|
|
|
if (std::error_code EC = BufferPtr.getError()) {
|
2018-04-18 17:26:51 +02:00
|
|
|
WithColor::error() << InputFilename << ": " << EC.message() << '\n';
|
2018-03-08 14:05:02 +01:00
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
2018-05-17 14:27:03 +02:00
|
|
|
// Apply overrides to llvm-mca specific options.
|
|
|
|
processViewOptions();
|
|
|
|
|
2018-03-08 14:05:02 +01:00
|
|
|
SourceMgr SrcMgr;
|
|
|
|
|
|
|
|
// Tell SrcMgr about this buffer, which is what the parser will pick up.
|
|
|
|
SrcMgr.AddNewSourceBuffer(std::move(*BufferPtr), SMLoc());
|
|
|
|
|
|
|
|
std::unique_ptr<MCRegisterInfo> MRI(TheTarget->createMCRegInfo(TripleName));
|
|
|
|
assert(MRI && "Unable to create target register info!");
|
|
|
|
|
|
|
|
std::unique_ptr<MCAsmInfo> MAI(TheTarget->createMCAsmInfo(*MRI, TripleName));
|
|
|
|
assert(MAI && "Unable to create target asm info!");
|
|
|
|
|
|
|
|
MCObjectFileInfo MOFI;
|
|
|
|
MCContext Ctx(MAI.get(), MRI.get(), &MOFI, &SrcMgr);
|
|
|
|
MOFI.InitMCObjectFileInfo(TheTriple, /* PIC= */ false, Ctx);
|
|
|
|
|
|
|
|
std::unique_ptr<buffer_ostream> BOS;
|
2018-03-26 14:04:53 +02:00
|
|
|
|
2018-03-08 14:05:02 +01:00
|
|
|
std::unique_ptr<MCInstrInfo> MCII(TheTarget->createMCInstrInfo());
|
2018-04-25 12:18:25 +02:00
|
|
|
|
2018-06-20 12:08:11 +02:00
|
|
|
std::unique_ptr<MCInstrAnalysis> MCIA(
|
|
|
|
TheTarget->createMCInstrAnalysis(MCII.get()));
|
|
|
|
|
2018-04-25 12:18:25 +02:00
|
|
|
if (!MCPU.compare("native"))
|
2018-11-08 19:08:43 +01:00
|
|
|
MCPU = llvm::sys::getHostCPUName();
|
2018-04-25 12:18:25 +02:00
|
|
|
|
2018-03-08 14:05:02 +01:00
|
|
|
std::unique_ptr<MCSubtargetInfo> STI(
|
|
|
|
TheTarget->createMCSubtargetInfo(TripleName, MCPU, /* FeaturesStr */ ""));
|
|
|
|
if (!STI->isCPUStringValid(MCPU))
|
|
|
|
return 1;
|
|
|
|
|
2018-04-30 14:05:34 +02:00
|
|
|
if (!PrintInstructionTables && !STI->getSchedModel().isOutOfOrder()) {
|
2018-04-18 17:26:51 +02:00
|
|
|
WithColor::error() << "please specify an out-of-order cpu. '" << MCPU
|
|
|
|
<< "' is an in-order cpu.\n";
|
2018-03-08 14:05:02 +01:00
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!STI->getSchedModel().hasInstrSchedModel()) {
|
2018-04-18 17:26:51 +02:00
|
|
|
WithColor::error()
|
|
|
|
<< "unable to find instruction-level scheduling information for"
|
2018-03-08 14:05:02 +01:00
|
|
|
<< " target triple '" << TheTriple.normalize() << "' and cpu '" << MCPU
|
|
|
|
<< "'.\n";
|
|
|
|
|
|
|
|
if (STI->getSchedModel().InstrItineraries)
|
2018-04-18 17:26:51 +02:00
|
|
|
WithColor::note()
|
|
|
|
<< "cpu '" << MCPU << "' provides itineraries. However, "
|
|
|
|
<< "instruction itineraries are currently unsupported.\n";
|
2018-03-08 14:05:02 +01:00
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
2018-11-07 20:20:04 +01:00
|
|
|
// Parse the input and create CodeRegions that llvm-mca can analyze.
|
|
|
|
mca::AsmCodeRegionGenerator CRG(*TheTarget, SrcMgr, Ctx, *MAI, *STI, *MCII);
|
|
|
|
Expected<const mca::CodeRegions &> RegionsOrErr = CRG.parseCodeRegions();
|
|
|
|
if (auto Err = RegionsOrErr.takeError()) {
|
|
|
|
WithColor::error() << Err << "\n";
|
2018-04-08 17:10:19 +02:00
|
|
|
return 1;
|
2018-11-07 20:20:04 +01:00
|
|
|
}
|
|
|
|
const mca::CodeRegions &Regions = *RegionsOrErr;
|
2018-04-09 18:39:52 +02:00
|
|
|
if (Regions.empty()) {
|
2018-04-18 17:26:51 +02:00
|
|
|
WithColor::error() << "no assembly instructions found.\n";
|
2018-03-08 14:05:02 +01:00
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
2018-03-08 17:08:43 +01:00
|
|
|
// Now initialize the output file.
|
|
|
|
auto OF = getOutputStream();
|
|
|
|
if (std::error_code EC = OF.getError()) {
|
2018-04-18 17:26:51 +02:00
|
|
|
WithColor::error() << EC.message() << '\n';
|
2018-03-08 17:08:43 +01:00
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
2018-11-07 20:20:04 +01:00
|
|
|
unsigned AssemblerDialect = CRG.getAssemblerDialect();
|
2018-04-24 18:19:08 +02:00
|
|
|
if (OutputAsmVariant >= 0)
|
|
|
|
AssemblerDialect = static_cast<unsigned>(OutputAsmVariant);
|
|
|
|
std::unique_ptr<MCInstPrinter> IP(TheTarget->createMCInstPrinter(
|
|
|
|
Triple(TripleName), AssemblerDialect, *MAI, *MCII, *MRI));
|
|
|
|
if (!IP) {
|
|
|
|
WithColor::error()
|
|
|
|
<< "unable to create instruction printer for target triple '"
|
|
|
|
<< TheTriple.normalize() << "' with assembly variant "
|
|
|
|
<< AssemblerDialect << ".\n";
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
2018-11-08 18:32:45 +01:00
|
|
|
std::unique_ptr<ToolOutputFile> TOF = std::move(*OF);
|
2018-03-08 17:08:43 +01:00
|
|
|
|
2018-03-08 14:05:02 +01:00
|
|
|
const MCSchedModel &SM = STI->getSchedModel();
|
|
|
|
|
|
|
|
unsigned Width = SM.IssueWidth;
|
|
|
|
if (DispatchWidth)
|
|
|
|
Width = DispatchWidth;
|
|
|
|
|
2018-03-23 12:50:43 +01:00
|
|
|
// Create an instruction builder.
|
2018-10-24 12:56:47 +02:00
|
|
|
mca::InstrBuilder IB(*STI, *MCII, *MRI, *MCIA);
|
2018-03-23 12:50:43 +01:00
|
|
|
|
2018-07-06 20:03:14 +02:00
|
|
|
// Create a context to control ownership of the pipeline hardware.
|
|
|
|
mca::Context MCA(*MRI, *STI);
|
|
|
|
|
|
|
|
mca::PipelineOptions PO(Width, RegisterFileSize, LoadQueueSize,
|
|
|
|
StoreQueueSize, AssumeNoAlias);
|
|
|
|
|
2018-04-09 18:39:52 +02:00
|
|
|
// Number each region in the sequence.
|
|
|
|
unsigned RegionIdx = 0;
|
2018-10-26 12:48:04 +02:00
|
|
|
|
2018-04-09 18:39:52 +02:00
|
|
|
for (const std::unique_ptr<mca::CodeRegion> &Region : Regions) {
|
|
|
|
// Skip empty code regions.
|
|
|
|
if (Region->empty())
|
|
|
|
continue;
|
|
|
|
|
|
|
|
// Don't print the header of this region if it is the default region, and
|
|
|
|
// it doesn't have an end location.
|
|
|
|
if (Region->startLoc().isValid() || Region->endLoc().isValid()) {
|
|
|
|
TOF->os() << "\n[" << RegionIdx++ << "] Code Region";
|
|
|
|
StringRef Desc = Region->getDescription();
|
|
|
|
if (!Desc.empty())
|
|
|
|
TOF->os() << " - " << Desc;
|
|
|
|
TOF->os() << "\n\n";
|
2018-03-26 15:44:54 +02:00
|
|
|
}
|
|
|
|
|
[llvm-mca] Lower to mca::Instructon before the pipeline is run.
Before this change, the lowering of instructions from llvm::MCInst to
mca::Instruction was done as part of the first stage of the pipeline (i.e. the
FetchStage). In particular, FetchStage was responsible for picking the next
instruction from the source sequence, and lower it to an mca::Instruction with
the help of an object of class InstrBuilder.
The dependency on InstrBuilder was problematic for a number of reasons. Class
InstrBuilder only knows how to lower from llvm::MCInst to mca::Instruction.
That means, it is hard to support a different scenario where instructions
in input are not instances of class llvm::MCInst. Even if we managed to
specialize InstrBuilder, and generalize most of its internal logic, the
dependency on InstrBuilder in FetchStage would have caused more troubles (other
than complicating the pipeline logic).
With this patch, the lowering step is done before the pipeline is run. The
pipeline is no longer responsible for lowering from MCInst to mca::Instruction.
As a consequence of this, the FetchStage no longer needs to interact with an
InstrBuilder. The mca::SourceMgr class now simply wraps a reference to a
sequence of mca::Instruction objects.
This simplifies the logic of FetchStage, and increases the usability of it. As
a result, on a debug build, we see a 7-9% speedup; on a release build, the
speedup is around 3-4%.
llvm-svn: 345500
2018-10-29 14:29:22 +01:00
|
|
|
// Lower the MCInst sequence into an mca::Instruction sequence.
|
2018-10-26 12:48:04 +02:00
|
|
|
ArrayRef<MCInst> Insts = Region->getInstructions();
|
[llvm-mca] Lower to mca::Instructon before the pipeline is run.
Before this change, the lowering of instructions from llvm::MCInst to
mca::Instruction was done as part of the first stage of the pipeline (i.e. the
FetchStage). In particular, FetchStage was responsible for picking the next
instruction from the source sequence, and lower it to an mca::Instruction with
the help of an object of class InstrBuilder.
The dependency on InstrBuilder was problematic for a number of reasons. Class
InstrBuilder only knows how to lower from llvm::MCInst to mca::Instruction.
That means, it is hard to support a different scenario where instructions
in input are not instances of class llvm::MCInst. Even if we managed to
specialize InstrBuilder, and generalize most of its internal logic, the
dependency on InstrBuilder in FetchStage would have caused more troubles (other
than complicating the pipeline logic).
With this patch, the lowering step is done before the pipeline is run. The
pipeline is no longer responsible for lowering from MCInst to mca::Instruction.
As a consequence of this, the FetchStage no longer needs to interact with an
InstrBuilder. The mca::SourceMgr class now simply wraps a reference to a
sequence of mca::Instruction objects.
This simplifies the logic of FetchStage, and increases the usability of it. As
a result, on a debug build, we see a 7-9% speedup; on a release build, the
speedup is around 3-4%.
llvm-svn: 345500
2018-10-29 14:29:22 +01:00
|
|
|
std::vector<std::unique_ptr<mca::Instruction>> LoweredSequence;
|
|
|
|
for (const MCInst &MCI : Insts) {
|
2018-11-08 18:32:45 +01:00
|
|
|
Expected<std::unique_ptr<mca::Instruction>> Inst =
|
2018-10-31 18:47:25 +01:00
|
|
|
IB.createInstruction(MCI);
|
[llvm-mca] Lower to mca::Instructon before the pipeline is run.
Before this change, the lowering of instructions from llvm::MCInst to
mca::Instruction was done as part of the first stage of the pipeline (i.e. the
FetchStage). In particular, FetchStage was responsible for picking the next
instruction from the source sequence, and lower it to an mca::Instruction with
the help of an object of class InstrBuilder.
The dependency on InstrBuilder was problematic for a number of reasons. Class
InstrBuilder only knows how to lower from llvm::MCInst to mca::Instruction.
That means, it is hard to support a different scenario where instructions
in input are not instances of class llvm::MCInst. Even if we managed to
specialize InstrBuilder, and generalize most of its internal logic, the
dependency on InstrBuilder in FetchStage would have caused more troubles (other
than complicating the pipeline logic).
With this patch, the lowering step is done before the pipeline is run. The
pipeline is no longer responsible for lowering from MCInst to mca::Instruction.
As a consequence of this, the FetchStage no longer needs to interact with an
InstrBuilder. The mca::SourceMgr class now simply wraps a reference to a
sequence of mca::Instruction objects.
This simplifies the logic of FetchStage, and increases the usability of it. As
a result, on a debug build, we see a 7-9% speedup; on a release build, the
speedup is around 3-4%.
llvm-svn: 345500
2018-10-29 14:29:22 +01:00
|
|
|
if (!Inst) {
|
2018-10-31 18:47:25 +01:00
|
|
|
if (auto NewE = handleErrors(
|
|
|
|
Inst.takeError(),
|
|
|
|
[&IP, &STI](const mca::InstructionError<MCInst> &IE) {
|
|
|
|
std::string InstructionStr;
|
|
|
|
raw_string_ostream SS(InstructionStr);
|
|
|
|
WithColor::error() << IE.Message << '\n';
|
|
|
|
IP->printInst(&IE.Inst, SS, "", *STI);
|
|
|
|
SS.flush();
|
|
|
|
WithColor::note() << "instruction: " << InstructionStr
|
|
|
|
<< '\n';
|
|
|
|
})) {
|
[llvm-mca] Lower to mca::Instructon before the pipeline is run.
Before this change, the lowering of instructions from llvm::MCInst to
mca::Instruction was done as part of the first stage of the pipeline (i.e. the
FetchStage). In particular, FetchStage was responsible for picking the next
instruction from the source sequence, and lower it to an mca::Instruction with
the help of an object of class InstrBuilder.
The dependency on InstrBuilder was problematic for a number of reasons. Class
InstrBuilder only knows how to lower from llvm::MCInst to mca::Instruction.
That means, it is hard to support a different scenario where instructions
in input are not instances of class llvm::MCInst. Even if we managed to
specialize InstrBuilder, and generalize most of its internal logic, the
dependency on InstrBuilder in FetchStage would have caused more troubles (other
than complicating the pipeline logic).
With this patch, the lowering step is done before the pipeline is run. The
pipeline is no longer responsible for lowering from MCInst to mca::Instruction.
As a consequence of this, the FetchStage no longer needs to interact with an
InstrBuilder. The mca::SourceMgr class now simply wraps a reference to a
sequence of mca::Instruction objects.
This simplifies the logic of FetchStage, and increases the usability of it. As
a result, on a debug build, we see a 7-9% speedup; on a release build, the
speedup is around 3-4%.
llvm-svn: 345500
2018-10-29 14:29:22 +01:00
|
|
|
// Default case.
|
|
|
|
WithColor::error() << toString(std::move(NewE));
|
|
|
|
}
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
LoweredSequence.emplace_back(std::move(Inst.get()));
|
|
|
|
}
|
|
|
|
|
2018-10-31 18:47:25 +01:00
|
|
|
mca::SourceMgr S(LoweredSequence, PrintInstructionTables ? 1 : Iterations);
|
2018-04-09 18:39:52 +02:00
|
|
|
|
|
|
|
if (PrintInstructionTables) {
|
2018-07-15 01:52:50 +02:00
|
|
|
// Create a pipeline, stages, and a printer.
|
2018-11-08 19:08:43 +01:00
|
|
|
auto P = llvm::make_unique<mca::Pipeline>();
|
|
|
|
P->appendStage(llvm::make_unique<mca::EntryStage>(S));
|
|
|
|
P->appendStage(llvm::make_unique<mca::InstructionTables>(SM));
|
2018-07-15 01:52:50 +02:00
|
|
|
mca::PipelinePrinter Printer(*P);
|
2018-04-09 18:39:52 +02:00
|
|
|
|
2018-07-15 01:52:50 +02:00
|
|
|
// Create the views for this pipeline, execute, and emit a report.
|
2018-04-09 18:39:52 +02:00
|
|
|
if (PrintInstructionInfoView) {
|
2018-11-08 19:08:43 +01:00
|
|
|
Printer.addView(llvm::make_unique<mca::InstructionInfoView>(
|
|
|
|
*STI, *MCII, Insts, *IP));
|
2018-04-09 18:39:52 +02:00
|
|
|
}
|
2018-11-08 19:08:43 +01:00
|
|
|
Printer.addView(
|
|
|
|
llvm::make_unique<mca::ResourcePressureView>(*STI, *IP, Insts));
|
2018-10-24 12:56:47 +02:00
|
|
|
|
[llvm-mca] Lower to mca::Instructon before the pipeline is run.
Before this change, the lowering of instructions from llvm::MCInst to
mca::Instruction was done as part of the first stage of the pipeline (i.e. the
FetchStage). In particular, FetchStage was responsible for picking the next
instruction from the source sequence, and lower it to an mca::Instruction with
the help of an object of class InstrBuilder.
The dependency on InstrBuilder was problematic for a number of reasons. Class
InstrBuilder only knows how to lower from llvm::MCInst to mca::Instruction.
That means, it is hard to support a different scenario where instructions
in input are not instances of class llvm::MCInst. Even if we managed to
specialize InstrBuilder, and generalize most of its internal logic, the
dependency on InstrBuilder in FetchStage would have caused more troubles (other
than complicating the pipeline logic).
With this patch, the lowering step is done before the pipeline is run. The
pipeline is no longer responsible for lowering from MCInst to mca::Instruction.
As a consequence of this, the FetchStage no longer needs to interact with an
InstrBuilder. The mca::SourceMgr class now simply wraps a reference to a
sequence of mca::Instruction objects.
This simplifies the logic of FetchStage, and increases the usability of it. As
a result, on a debug build, we see a 7-9% speedup; on a release build, the
speedup is around 3-4%.
llvm-svn: 345500
2018-10-29 14:29:22 +01:00
|
|
|
if (!runPipeline(*P))
|
2018-10-24 12:56:47 +02:00
|
|
|
return 1;
|
|
|
|
|
2018-07-15 01:52:50 +02:00
|
|
|
Printer.printReport(TOF->os());
|
2018-04-09 18:39:52 +02:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2018-07-06 20:03:14 +02:00
|
|
|
// Create a basic pipeline simulating an out-of-order backend.
|
|
|
|
auto P = MCA.createDefaultPipeline(PO, IB, S);
|
2018-06-25 18:53:00 +02:00
|
|
|
mca::PipelinePrinter Printer(*P);
|
2018-03-09 14:52:03 +01:00
|
|
|
|
2018-06-15 16:01:43 +02:00
|
|
|
if (PrintSummaryView)
|
2018-11-08 19:08:43 +01:00
|
|
|
Printer.addView(llvm::make_unique<mca::SummaryView>(SM, Insts, Width));
|
2018-06-15 16:01:43 +02:00
|
|
|
|
2018-04-09 18:39:52 +02:00
|
|
|
if (PrintInstructionInfoView)
|
|
|
|
Printer.addView(
|
2018-11-08 19:08:43 +01:00
|
|
|
llvm::make_unique<mca::InstructionInfoView>(*STI, *MCII, Insts, *IP));
|
2018-03-23 20:40:04 +01:00
|
|
|
|
2018-04-10 16:55:14 +02:00
|
|
|
if (PrintDispatchStats)
|
2018-11-08 19:08:43 +01:00
|
|
|
Printer.addView(llvm::make_unique<mca::DispatchStatistics>());
|
2018-04-10 16:55:14 +02:00
|
|
|
|
2018-04-11 14:12:53 +02:00
|
|
|
if (PrintSchedulerStats)
|
2018-11-08 19:08:43 +01:00
|
|
|
Printer.addView(llvm::make_unique<mca::SchedulerStatistics>(*STI));
|
2018-04-11 13:37:46 +02:00
|
|
|
|
2018-04-11 14:12:53 +02:00
|
|
|
if (PrintRetireStats)
|
2018-11-23 13:12:57 +01:00
|
|
|
Printer.addView(llvm::make_unique<mca::RetireControlUnitStatistics>(SM));
|
2018-03-08 17:08:43 +01:00
|
|
|
|
2018-04-09 18:39:52 +02:00
|
|
|
if (PrintRegisterFileStats)
|
2018-11-08 19:08:43 +01:00
|
|
|
Printer.addView(llvm::make_unique<mca::RegisterFileStatistics>(*STI));
|
2018-03-08 17:08:43 +01:00
|
|
|
|
2018-04-09 18:39:52 +02:00
|
|
|
if (PrintResourcePressureView)
|
2018-11-08 19:08:43 +01:00
|
|
|
Printer.addView(
|
|
|
|
llvm::make_unique<mca::ResourcePressureView>(*STI, *IP, Insts));
|
2018-04-03 18:46:23 +02:00
|
|
|
|
2018-04-09 18:39:52 +02:00
|
|
|
if (PrintTimelineView) {
|
2018-10-26 12:48:04 +02:00
|
|
|
unsigned TimelineIterations =
|
|
|
|
TimelineMaxIterations ? TimelineMaxIterations : 10;
|
2018-11-08 19:08:43 +01:00
|
|
|
Printer.addView(llvm::make_unique<mca::TimelineView>(
|
2018-10-26 12:48:04 +02:00
|
|
|
*STI, *IP, Insts, std::min(TimelineIterations, S.getNumIterations()),
|
|
|
|
TimelineMaxCycles));
|
2018-04-09 18:39:52 +02:00
|
|
|
}
|
2018-03-08 17:08:43 +01:00
|
|
|
|
[llvm-mca] Lower to mca::Instructon before the pipeline is run.
Before this change, the lowering of instructions from llvm::MCInst to
mca::Instruction was done as part of the first stage of the pipeline (i.e. the
FetchStage). In particular, FetchStage was responsible for picking the next
instruction from the source sequence, and lower it to an mca::Instruction with
the help of an object of class InstrBuilder.
The dependency on InstrBuilder was problematic for a number of reasons. Class
InstrBuilder only knows how to lower from llvm::MCInst to mca::Instruction.
That means, it is hard to support a different scenario where instructions
in input are not instances of class llvm::MCInst. Even if we managed to
specialize InstrBuilder, and generalize most of its internal logic, the
dependency on InstrBuilder in FetchStage would have caused more troubles (other
than complicating the pipeline logic).
With this patch, the lowering step is done before the pipeline is run. The
pipeline is no longer responsible for lowering from MCInst to mca::Instruction.
As a consequence of this, the FetchStage no longer needs to interact with an
InstrBuilder. The mca::SourceMgr class now simply wraps a reference to a
sequence of mca::Instruction objects.
This simplifies the logic of FetchStage, and increases the usability of it. As
a result, on a debug build, we see a 7-9% speedup; on a release build, the
speedup is around 3-4%.
llvm-svn: 345500
2018-10-29 14:29:22 +01:00
|
|
|
if (!runPipeline(*P))
|
2018-10-24 12:56:47 +02:00
|
|
|
return 1;
|
|
|
|
|
2018-04-09 18:39:52 +02:00
|
|
|
Printer.printReport(TOF->os());
|
2018-07-02 22:39:57 +02:00
|
|
|
|
|
|
|
// Clear the InstrBuilder internal state in preparation for another round.
|
|
|
|
IB.clear();
|
2018-03-08 17:08:43 +01:00
|
|
|
}
|
2018-03-08 14:05:02 +01:00
|
|
|
|
2018-03-08 17:08:43 +01:00
|
|
|
TOF->keep();
|
2018-03-08 14:05:02 +01:00
|
|
|
return 0;
|
|
|
|
}
|