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llvm-mirror/test/CodeGen/RISCV/fp-imm.ll

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[NFC][RISCV] Test for 0.0 fp immediate To show a later change that impacts 0.0 fp constant generation. Differential Revision: https://reviews.llvm.org/D75728
2020-03-20 09:31:59 +01:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+f < %s \
; RUN: | FileCheck --check-prefix=RV32F %s
; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+f,+d < %s \
; RUN: | FileCheck --check-prefix=RV32D %s
; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+f < %s \
; RUN: | FileCheck --check-prefix=RV64F %s
; RUN: llc -mtriple=riscv64 -target-abi lp64d -mattr=+f,+d < %s \
; RUN: | FileCheck --check-prefix=RV64D %s
define float @f32_positive_zero(float *%pf) nounwind {
; RV32F-LABEL: f32_positive_zero:
; RV32F: # %bb.0:
[RISCV] Select +0.0 immediate using fmv.{w,d}.x / fcvt.d.w Floating point positive zero can be selected using fmv.w.x / fmv.d.x / fcvt.d.w and the zero source register. Differential Revision: https://reviews.llvm.org/D75729
2020-03-20 10:22:48 +01:00
; RV32F-NEXT: fmv.w.x fa0, zero
[NFC][RISCV] Test for 0.0 fp immediate To show a later change that impacts 0.0 fp constant generation. Differential Revision: https://reviews.llvm.org/D75728
2020-03-20 09:31:59 +01:00
; RV32F-NEXT: ret
;
; RV32D-LABEL: f32_positive_zero:
; RV32D: # %bb.0:
[RISCV] Select +0.0 immediate using fmv.{w,d}.x / fcvt.d.w Floating point positive zero can be selected using fmv.w.x / fmv.d.x / fcvt.d.w and the zero source register. Differential Revision: https://reviews.llvm.org/D75729
2020-03-20 10:22:48 +01:00
; RV32D-NEXT: fmv.w.x fa0, zero
[NFC][RISCV] Test for 0.0 fp immediate To show a later change that impacts 0.0 fp constant generation. Differential Revision: https://reviews.llvm.org/D75728
2020-03-20 09:31:59 +01:00
; RV32D-NEXT: ret
;
; RV64F-LABEL: f32_positive_zero:
; RV64F: # %bb.0:
[RISCV] Select +0.0 immediate using fmv.{w,d}.x / fcvt.d.w Floating point positive zero can be selected using fmv.w.x / fmv.d.x / fcvt.d.w and the zero source register. Differential Revision: https://reviews.llvm.org/D75729
2020-03-20 10:22:48 +01:00
; RV64F-NEXT: fmv.w.x fa0, zero
[NFC][RISCV] Test for 0.0 fp immediate To show a later change that impacts 0.0 fp constant generation. Differential Revision: https://reviews.llvm.org/D75728
2020-03-20 09:31:59 +01:00
; RV64F-NEXT: ret
;
; RV64D-LABEL: f32_positive_zero:
; RV64D: # %bb.0:
[RISCV] Select +0.0 immediate using fmv.{w,d}.x / fcvt.d.w Floating point positive zero can be selected using fmv.w.x / fmv.d.x / fcvt.d.w and the zero source register. Differential Revision: https://reviews.llvm.org/D75729
2020-03-20 10:22:48 +01:00
; RV64D-NEXT: fmv.w.x fa0, zero
[NFC][RISCV] Test for 0.0 fp immediate To show a later change that impacts 0.0 fp constant generation. Differential Revision: https://reviews.llvm.org/D75728
2020-03-20 09:31:59 +01:00
; RV64D-NEXT: ret
ret float 0.0
}
define float @f32_negative_zero(float *%pf) nounwind {
; RV32F-LABEL: f32_negative_zero:
; RV32F: # %bb.0:
; RV32F-NEXT: lui a0, %hi(.LCPI1_0)
[RISCV] Support Constant Pools in Load/Store Peephole Summary: RISC-V uses a post-select peephole pass to optimise `(load/store (ADDI $reg, %lo(addr)), 0)` into `(load/store $reg, %lo(addr))`. This peephole wasn't firing for accesses to constant pools, which is how we materialise most floating point constants. This adds support for the constantpool case, which improves code generation for lots of small FP loading examples. I have not added any tests because this structure is well-covered by the `fp-imm.ll` testcases, as well as almost all other uses of floating point constants in the RISC-V backend tests. Reviewed By: luismarques, asb Differential Revision: https://reviews.llvm.org/D79523
2020-05-11 19:52:42 +02:00
; RV32F-NEXT: flw fa0, %lo(.LCPI1_0)(a0)
[NFC][RISCV] Test for 0.0 fp immediate To show a later change that impacts 0.0 fp constant generation. Differential Revision: https://reviews.llvm.org/D75728
2020-03-20 09:31:59 +01:00
; RV32F-NEXT: ret
;
; RV32D-LABEL: f32_negative_zero:
; RV32D: # %bb.0:
; RV32D-NEXT: lui a0, %hi(.LCPI1_0)
[RISCV] Support Constant Pools in Load/Store Peephole Summary: RISC-V uses a post-select peephole pass to optimise `(load/store (ADDI $reg, %lo(addr)), 0)` into `(load/store $reg, %lo(addr))`. This peephole wasn't firing for accesses to constant pools, which is how we materialise most floating point constants. This adds support for the constantpool case, which improves code generation for lots of small FP loading examples. I have not added any tests because this structure is well-covered by the `fp-imm.ll` testcases, as well as almost all other uses of floating point constants in the RISC-V backend tests. Reviewed By: luismarques, asb Differential Revision: https://reviews.llvm.org/D79523
2020-05-11 19:52:42 +02:00
; RV32D-NEXT: flw fa0, %lo(.LCPI1_0)(a0)
[NFC][RISCV] Test for 0.0 fp immediate To show a later change that impacts 0.0 fp constant generation. Differential Revision: https://reviews.llvm.org/D75728
2020-03-20 09:31:59 +01:00
; RV32D-NEXT: ret
;
; RV64F-LABEL: f32_negative_zero:
; RV64F: # %bb.0:
; RV64F-NEXT: lui a0, %hi(.LCPI1_0)
[RISCV] Support Constant Pools in Load/Store Peephole Summary: RISC-V uses a post-select peephole pass to optimise `(load/store (ADDI $reg, %lo(addr)), 0)` into `(load/store $reg, %lo(addr))`. This peephole wasn't firing for accesses to constant pools, which is how we materialise most floating point constants. This adds support for the constantpool case, which improves code generation for lots of small FP loading examples. I have not added any tests because this structure is well-covered by the `fp-imm.ll` testcases, as well as almost all other uses of floating point constants in the RISC-V backend tests. Reviewed By: luismarques, asb Differential Revision: https://reviews.llvm.org/D79523
2020-05-11 19:52:42 +02:00
; RV64F-NEXT: flw fa0, %lo(.LCPI1_0)(a0)
[NFC][RISCV] Test for 0.0 fp immediate To show a later change that impacts 0.0 fp constant generation. Differential Revision: https://reviews.llvm.org/D75728
2020-03-20 09:31:59 +01:00
; RV64F-NEXT: ret
;
; RV64D-LABEL: f32_negative_zero:
; RV64D: # %bb.0:
; RV64D-NEXT: lui a0, %hi(.LCPI1_0)
[RISCV] Support Constant Pools in Load/Store Peephole Summary: RISC-V uses a post-select peephole pass to optimise `(load/store (ADDI $reg, %lo(addr)), 0)` into `(load/store $reg, %lo(addr))`. This peephole wasn't firing for accesses to constant pools, which is how we materialise most floating point constants. This adds support for the constantpool case, which improves code generation for lots of small FP loading examples. I have not added any tests because this structure is well-covered by the `fp-imm.ll` testcases, as well as almost all other uses of floating point constants in the RISC-V backend tests. Reviewed By: luismarques, asb Differential Revision: https://reviews.llvm.org/D79523
2020-05-11 19:52:42 +02:00
; RV64D-NEXT: flw fa0, %lo(.LCPI1_0)(a0)
[NFC][RISCV] Test for 0.0 fp immediate To show a later change that impacts 0.0 fp constant generation. Differential Revision: https://reviews.llvm.org/D75728
2020-03-20 09:31:59 +01:00
; RV64D-NEXT: ret
ret float -0.0
}
define double @f64_positive_zero(double *%pd) nounwind {
; RV32F-LABEL: f64_positive_zero:
; RV32F: # %bb.0:
; RV32F-NEXT: mv a0, zero
; RV32F-NEXT: mv a1, zero
; RV32F-NEXT: ret
;
; RV32D-LABEL: f64_positive_zero:
; RV32D: # %bb.0:
[RISCV] Select +0.0 immediate using fmv.{w,d}.x / fcvt.d.w Floating point positive zero can be selected using fmv.w.x / fmv.d.x / fcvt.d.w and the zero source register. Differential Revision: https://reviews.llvm.org/D75729
2020-03-20 10:22:48 +01:00
; RV32D-NEXT: fcvt.d.w fa0, zero
[NFC][RISCV] Test for 0.0 fp immediate To show a later change that impacts 0.0 fp constant generation. Differential Revision: https://reviews.llvm.org/D75728
2020-03-20 09:31:59 +01:00
; RV32D-NEXT: ret
;
; RV64F-LABEL: f64_positive_zero:
; RV64F: # %bb.0:
; RV64F-NEXT: mv a0, zero
; RV64F-NEXT: ret
;
; RV64D-LABEL: f64_positive_zero:
; RV64D: # %bb.0:
[RISCV] Select +0.0 immediate using fmv.{w,d}.x / fcvt.d.w Floating point positive zero can be selected using fmv.w.x / fmv.d.x / fcvt.d.w and the zero source register. Differential Revision: https://reviews.llvm.org/D75729
2020-03-20 10:22:48 +01:00
; RV64D-NEXT: fmv.d.x fa0, zero
[NFC][RISCV] Test for 0.0 fp immediate To show a later change that impacts 0.0 fp constant generation. Differential Revision: https://reviews.llvm.org/D75728
2020-03-20 09:31:59 +01:00
; RV64D-NEXT: ret
ret double 0.0
}
define double @f64_negative_zero(double *%pd) nounwind {
; RV32F-LABEL: f64_negative_zero:
; RV32F: # %bb.0:
; RV32F-NEXT: lui a1, 524288
; RV32F-NEXT: mv a0, zero
; RV32F-NEXT: ret
;
; RV32D-LABEL: f64_negative_zero:
; RV32D: # %bb.0:
; RV32D-NEXT: lui a0, %hi(.LCPI3_0)
[RISCV] Support Constant Pools in Load/Store Peephole Summary: RISC-V uses a post-select peephole pass to optimise `(load/store (ADDI $reg, %lo(addr)), 0)` into `(load/store $reg, %lo(addr))`. This peephole wasn't firing for accesses to constant pools, which is how we materialise most floating point constants. This adds support for the constantpool case, which improves code generation for lots of small FP loading examples. I have not added any tests because this structure is well-covered by the `fp-imm.ll` testcases, as well as almost all other uses of floating point constants in the RISC-V backend tests. Reviewed By: luismarques, asb Differential Revision: https://reviews.llvm.org/D79523
2020-05-11 19:52:42 +02:00
; RV32D-NEXT: fld fa0, %lo(.LCPI3_0)(a0)
[NFC][RISCV] Test for 0.0 fp immediate To show a later change that impacts 0.0 fp constant generation. Differential Revision: https://reviews.llvm.org/D75728
2020-03-20 09:31:59 +01:00
; RV32D-NEXT: ret
;
; RV64F-LABEL: f64_negative_zero:
; RV64F: # %bb.0:
; RV64F-NEXT: addi a0, zero, -1
; RV64F-NEXT: slli a0, a0, 63
; RV64F-NEXT: ret
;
; RV64D-LABEL: f64_negative_zero:
; RV64D: # %bb.0:
; RV64D-NEXT: lui a0, %hi(.LCPI3_0)
[RISCV] Support Constant Pools in Load/Store Peephole Summary: RISC-V uses a post-select peephole pass to optimise `(load/store (ADDI $reg, %lo(addr)), 0)` into `(load/store $reg, %lo(addr))`. This peephole wasn't firing for accesses to constant pools, which is how we materialise most floating point constants. This adds support for the constantpool case, which improves code generation for lots of small FP loading examples. I have not added any tests because this structure is well-covered by the `fp-imm.ll` testcases, as well as almost all other uses of floating point constants in the RISC-V backend tests. Reviewed By: luismarques, asb Differential Revision: https://reviews.llvm.org/D79523
2020-05-11 19:52:42 +02:00
; RV64D-NEXT: fld fa0, %lo(.LCPI3_0)(a0)
[NFC][RISCV] Test for 0.0 fp immediate To show a later change that impacts 0.0 fp constant generation. Differential Revision: https://reviews.llvm.org/D75728
2020-03-20 09:31:59 +01:00
; RV64D-NEXT: ret
ret double -0.0
}
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