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[RISCV] Remove unused ComplexPatterns. NFC
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@ -1448,21 +1448,6 @@ bool RISCVDAGToDAGISel::selectRVVSimm5(SDValue N, unsigned Width,
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return false;
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}
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bool RISCVDAGToDAGISel::selectRVVUimm5(SDValue N, unsigned Width,
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SDValue &Imm) {
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if (auto *C = dyn_cast<ConstantSDNode>(N)) {
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int64_t ImmVal = C->getSExtValue();
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if (!isUInt<5>(ImmVal))
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return false;
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Imm = CurDAG->getTargetConstant(ImmVal, SDLoc(N), Subtarget->getXLenVT());
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return true;
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}
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return false;
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}
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// Merge an ADDI into the offset of a load/store instruction where possible.
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// (load (addi base, off1), off2) -> (load base, off1+off2)
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// (store val, (addi base, off1), off2) -> (store val, base, off1+off2)
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@ -74,11 +74,6 @@ public:
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return selectRVVSimm5(N, Width, Imm);
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}
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bool selectRVVUimm5(SDValue N, unsigned Width, SDValue &Imm);
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template <unsigned Width> bool selectRVVUimm5(SDValue N, SDValue &Imm) {
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return selectRVVUimm5(N, Width, Imm);
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}
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void addVectorLoadStoreOperands(SDNode *Node, unsigned SEWImm,
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const SDLoc &DL, unsigned CurOp,
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bool IsMasked, bool IsStridedOrIndexed,
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@ -233,11 +233,6 @@ def sew16simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<16>", []>;
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def sew32simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<32>", []>;
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def sew64simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<64>", []>;
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def sew8uimm5 : ComplexPattern<XLenVT, 1, "selectRVVUimm5<8>", []>;
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def sew16uimm5 : ComplexPattern<XLenVT, 1, "selectRVVUimm5<16>", []>;
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def sew32uimm5 : ComplexPattern<XLenVT, 1, "selectRVVUimm5<32>", []>;
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def sew64uimm5 : ComplexPattern<XLenVT, 1, "selectRVVUimm5<64>", []>;
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multiclass VPatBinaryVL_VV<SDNode vop,
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string instruction_name,
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ValueType result_type,
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