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[AArch64][GlobalISel] Enable CSE for the prelegalizer combiner.
Differential Revision: https://reviews.llvm.org/D95647
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@ -205,6 +205,8 @@ void AArch64PreLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<MachineDominatorTree>();
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AU.addPreserved<MachineDominatorTree>();
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}
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AU.addRequired<GISelCSEAnalysisWrapperPass>();
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AU.addPreserved<GISelCSEAnalysisWrapperPass>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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@ -217,7 +219,13 @@ bool AArch64PreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
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if (MF.getProperties().hasProperty(
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MachineFunctionProperties::Property::FailedISel))
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return false;
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auto *TPC = &getAnalysis<TargetPassConfig>();
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auto &TPC = getAnalysis<TargetPassConfig>();
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// Enable CSE.
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GISelCSEAnalysisWrapper &Wrapper =
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getAnalysis<GISelCSEAnalysisWrapperPass>().getCSEWrapper();
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auto *CSEInfo = &Wrapper.get(TPC.getCSEConfig());
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const Function &F = MF.getFunction();
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bool EnableOpt =
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MF.getTarget().getOptLevel() != CodeGenOpt::None && !skipFunction(F);
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@ -226,8 +234,8 @@ bool AArch64PreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
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IsOptNone ? nullptr : &getAnalysis<MachineDominatorTree>();
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AArch64PreLegalizerCombinerInfo PCInfo(EnableOpt, F.hasOptSize(),
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F.hasMinSize(), KB, MDT);
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Combiner C(PCInfo, TPC);
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return C.combineMachineInstrs(MF, /*CSEInfo*/ nullptr);
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Combiner C(PCInfo, &TPC);
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return C.combineMachineInstrs(MF, CSEInfo);
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}
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char AArch64PreLegalizerCombiner::ID = 0;
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@ -236,6 +244,7 @@ INITIALIZE_PASS_BEGIN(AArch64PreLegalizerCombiner, DEBUG_TYPE,
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false, false)
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INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
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INITIALIZE_PASS_DEPENDENCY(GISelKnownBitsAnalysis)
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INITIALIZE_PASS_DEPENDENCY(GISelCSEAnalysisWrapperPass)
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INITIALIZE_PASS_END(AArch64PreLegalizerCombiner, DEBUG_TYPE,
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"Combine AArch64 machine instrs before legalization", false,
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false)
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@ -11,16 +11,16 @@ body: |
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; CHECK: bb.0:
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; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK: liveins: $x0
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; CHECK: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
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; CHECK: [[DEF:%[0-9]+]]:_(s1) = G_IMPLICIT_DEF
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; CHECK: [[DEF1:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 9
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; CHECK: [[DEF1:%[0-9]+]]:_(s1) = G_IMPLICIT_DEF
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; CHECK: G_BRCOND [[DEF1]](s1), %bb.2
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; CHECK: G_BRCOND [[DEF]](s1), %bb.2
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; CHECK: G_BR %bb.1
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; CHECK: bb.1:
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; CHECK: successors:
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; CHECK: bb.2:
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; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p0) :: (load 4 from `i32* undef`, align 8)
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; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[DEF1]](p0) :: (load 4 from `i32* undef`, align 8)
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; CHECK: [[MUL:%[0-9]+]]:_(s32) = nsw G_MUL [[C]], [[LOAD]]
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; CHECK: [[MUL1:%[0-9]+]]:_(s32) = nsw G_MUL [[MUL]], [[C1]]
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; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
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@ -56,9 +56,9 @@
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; VERIFY-NEXT: Verify generated machine code
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; ENABLED-NEXT: Analysis for ComputingKnownBits
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; ENABLED-O1-NEXT: MachineDominator Tree Construction
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; ENABLED-NEXT: Analysis containing CSE Info
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; ENABLED-NEXT: PreLegalizerCombiner
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; VERIFY-NEXT: Verify generated machine code
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; ENABLED-NEXT: Analysis containing CSE Info
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; ENABLED-NEXT: Legalizer
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; VERIFY-NEXT: Verify generated machine code
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; ENABLED: RegBankSelect
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@ -34,8 +34,8 @@
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; CHECK-NEXT: Analysis containing CSE Info
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; CHECK-NEXT: IRTranslator
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; CHECK-NEXT: Analysis for ComputingKnownBits
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; CHECK-NEXT: AArch64PreLegalizerCombiner
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; CHECK-NEXT: Analysis containing CSE Info
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; CHECK-NEXT: AArch64PreLegalizerCombiner
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; CHECK-NEXT: Legalizer
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; CHECK-NEXT: AArch64PostLegalizerLowering
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; CHECK-NEXT: RegBankSelect
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